Phase-Coherent Signal Generator Using Timed Phase Loading

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Solution Overview

Problem

Conventional phase-locked loops (PLLs) lose initial phase information upon reset or reinitialization, resulting in non-coherent source signals, which complicates applications requiring coherent signals and increases system complexity, power consumption, and cost.

Innovation Solution

A signal generator with a phase setting circuit and memory circuit that loads a phase setting value at specific times to control the phase of the source signal, allowing for coherent phase maintenance across different operational periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple PLLs are used to achieve phase coherency, then phase coherence is maintained, but device complexity increases

Engineering Contradiction:
Improvephase coherenceVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing phase setting values in a memory circuit before signal generation. When the signal generator is reinitialized, it loads the pre-computed phase setting value from memory, which determines the initial phase of the VCO. This ensures that the phase trajectory is coherent with previous operations without requiring multiple PLLs, thus maintaining phase coherence while reducing system complexity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple PLLs are used to achieve phase coherency, then phase coherence is maintained, but power consumption increases

Engineering Contradiction:
Improvephase coherenceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent computes and stores the required phase setting values in advance in a memory circuit. During operation, the system simply retrieves the pre-computed value from memory and loads it into the phase setting circuit, rather than maintaining multiple active PLLs. This preliminary computation approach significantly reduces power consumption while ensuring phase coherence is maintained across reinitialization events.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If PLL is reset or settings are changed, then system is reinitialized, but phase coherence is lost

Engineering Contradiction:
Improvereinitialization capabilityVSAvoidphase coherence
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent stores pre-computed phase setting values in a memory circuit before reinitialization occurs. When the PLL is reset or settings are changed, the system loads the appropriate phase setting value from memory, which was pre-calculated to ensure coherent phase trajectory. This allows the system to be reinitialized while maintaining phase coherence with previous operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where the phase setting value stored in memory is determined based on the phase trajectory of previously generated signals. The system uses information about the original phase trajectory to compute and store the correct phase setting value that will maintain coherence upon reinitialization, creating a feedback loop that preserves phase information.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10886905B1Signal generator with coherent phase output
Publication Date: 2021.01.05 DIALOG SEMICONDUCTOR BV
  • US10886905B1 patent drawing
  • US10886905B1 patent drawing
  • US10886905B1 patent drawing

AI summary

A signal generator and a method which provides a source signal with a coherent phase at arbitrary times is presented. There is provided a signal generator for generating a source signal based on a reference signal. The signal generator has a phase setting circuit with a memory circuit operable between a plurality of states. The memory circuit has a phase setting input adapted to receive a phase setting value to set the memory circuit to a known state. The signal generator is adapted to load the phase setting value at a specific time to control a phase of the source signal.