Phase Comparator Using Reference Clock Delay for Stable CDR
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Solution Overview
Problem
Existing phase comparison techniques in data communication are susceptible to fluctuations in power supply voltage and temperature, requiring precise delay elements that increase circuit area and power consumption, and necessitate multiple clock phases, leading to wiring issues and signal degradation.
Innovation Solution
A phase comparator that detects the presence or absence of data signal transitions during a defined comparison period, using a reference clock signal with a phase delayed from the primary clock signal, eliminating the need for delay elements and reducing the number of required clock signals, thereby stabilizing the phase comparison process and minimizing wiring and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precise delay elements are used to achieve stable phase comparison, then phase comparison stability is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the delay element from the phase comparison circuit. Instead of using a delay element to delay the data signal, the invention uses a reference clock signal that is externally provided with a predetermined phase delay. This removes the need for internal delay elements, reducing circuit area while maintaining phase comparison stability.
Solution Approach 2:
The patent introduces a reference clock signal as an intermediary to achieve phase delay. Rather than delaying the data signal directly through a delay element, the system uses the reference clock signal (which already has the required phase delay) as a mediator to define the comparison period. This intermediary approach eliminates the need for precision delay elements while maintaining stable phase comparison.
2Measurement precision
If multiple clock phases are used to achieve stable phase comparison, then phase comparison accuracy is improved, but wiring area and signal degradation increase
Solution Approach 1:
The patent extracts and eliminates the multi-phase clock generation circuit from the system. Instead of generating multiple clock phases internally, the invention uses a single reference clock signal that is externally provided with the appropriate phase characteristics. This removes the complex wiring required for distributing multiple clock phases while maintaining phase comparison accuracy.
Solution Approach 2:
The reference clock signal serves multiple functions: it provides the timing reference for phase comparison, incorporates the necessary phase delay, and eliminates the need for separate multi-phase clock distribution wiring. This multi-functional approach reduces wiring area while maintaining measurement precision.
3Reliability
If multiple clock signals are used for phase comparison, then phase detection capability is improved, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates the need for multiple clock signals by using a single reference clock signal with predetermined phase characteristics. This reduces the power consumption associated with generating and distributing multiple clock signals while maintaining phase detection capability through the use of the reference clock for defining the comparison period.
4Ease of operation
If delay elements are used to define comparison period, then phase comparison functionality is achieved, but susceptibility to voltage and temperature fluctuations increases
Solution Approach 1:
The patent extracts and removes the delay element from the phase comparison circuit. By using a reference clock signal with predetermined phase delay instead of a delay element, the system eliminates the component that is susceptible to voltage and temperature fluctuations, thereby improving reliability while maintaining phase comparison functionality.
Solution Approach 2:
The reference clock signal acts as an intermediary that provides the necessary phase delay without being susceptible to environmental fluctuations. This mediator approach replaces the vulnerable delay element while maintaining the phase comparison functionality through the externally provided reference clock with stable phase characteristics.
Data Source
AI summary
A comparison period detecting unit (11) defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the comparison period. A phase relationship detecting unit (12) detects a phase relationship between the data signal and a reference clock signal, and outputs a result of detection of the phase relationship when the comparison period detecting unit (11) detects transition of the data signal during the comparison period.