Phase Comparator for High-Speed I/O Testing
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Solution Overview
Problem
Conventional testing techniques for high-speed digital input-output (I/O) circuits in electronic devices are inefficient due to high costs, complex on-chip test circuits, and inadequate testing of receiver circuits, which occupy significant die area and consume excessive power.
Innovation Solution
A test system and method that utilize a phase tracking circuit with a phase comparator outputting a phase signal externally to minimize die area and power consumption, allowing effective testing of both transmitter and receiver circuits by generating bit-level data for parametric analysis, and using data reduction techniques to facilitate remote testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional on-chip test circuits are used to test high-speed I/O circuits, then testing capability is improved, but die area occupation and power consumption increase significantly
Solution Approach 1:
The patent extracts the test circuit functionality from the main chip by using a separate programmable logic device (PLD) or field-programmable gate array (FPGA) as an external test interface. This external test circuit communicates with the I/O circuit under test through the same transmission medium, allowing comprehensive testing without occupying additional die area on the main chip.
Solution Approach 2:
The patent creates a universal test interface that can test multiple types of I/O circuits (transmitters, receivers, equalizers) using a single external test system. The programmable logic device can be configured to perform different test functions, making the testing system adaptable to various I/O circuit designs without requiring dedicated test circuits for each type.
2Reliability
If conventional on-chip test circuits are used to test high-speed I/O circuits, then testing capability is improved, but power consumption increases excessively
Solution Approach 1:
By moving the test circuit functionality to an external programmable logic device, the patent eliminates the need for power-consuming on-chip test circuits. The external test system draws power separately and only activates during testing, rather than continuously consuming power as part of the main chip operation.
Solution Approach 2:
The testing is performed periodically or on-demand rather than continuously. The external test interface can be enabled only when testing is required, allowing the I/O circuits to operate normally without test overhead during regular operation, thus minimizing overall power consumption.
3Reliability
If receiver circuits are tested using conventional techniques, then transmitter testing is covered, but receiver circuit testing is inadequate due to lack of test access
Solution Approach 1:
The patent introduces an intermediary test interface that provides controlled access to the receiver circuit outputs. This intermediate layer allows the external test system to safely and effectively measure receiver output signals without requiring direct modification of the receiver circuit architecture or adding complex on-chip test access mechanisms.
Solution Approach 2:
Instead of trying to access receiver internal signals directly, the patent inverts the approach by testing the receiver through its output interface. The external test system applies stimuli and measures the resulting output signals, effectively characterizing receiver performance without needing direct internal access points.
4Measurement precision
If comprehensive I/O circuit testing is performed, then testing accuracy is improved, but testing cost increases due to time and equipment resources
Solution Approach 1:
The patent performs preliminary configuration of the external test interface using programmable logic devices. Test sequences, stimulus patterns, and measurement parameters can be pre-programmed and loaded before actual testing begins, allowing comprehensive tests to execute efficiently without requiring complex real-time setup or manual intervention during testing.
5Reliability
If on-chip test circuits are added to effectively test I/O circuits, then testing capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts all complex test circuit functionality from the main I/O device chip and relocates it to external programmable logic devices. This separation maintains simple, clean I/O circuit design while providing comprehensive testing capabilities through the external interface, avoiding the need to integrate complex test logic into the main device architecture.
Solution Approach 2:
The external test interface creates a virtual model or copy of the I/O circuit behavior through programmable logic. Rather than adding physical test circuits to the chip, the external system simulates and measures I/O circuit responses, providing comprehensive testing without modifying or complicating the actual device design.
Data Source
AI summary
A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator; and determining parametric information pertaining to the I/O circuit of the device under test from the phase signal.