Phase Comparing Circuit With Coincidence Control Against Metastability
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Solution Overview
Problem
The increasing operation frequency of DRAMs makes it difficult to provide sufficient delay time to prevent metastable phenomena in phase comparing circuits, leading to a high probability of erroneous operations in connected circuits.
Innovation Solution
A phase comparing circuit design that includes a first storage circuit, multiple inverter circuits with different threshold levels, a delay circuit, and a coincidence control circuit to reduce delay time while preventing erroneous operations, utilizing inverters with hysteresis characteristics and current mirror amplifiers for precise threshold control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay time is increased to prevent metastable phenomena, then reliability is improved, but operation frequency is reduced
Solution Approach 1:
The patent divides the phase comparing circuit into multiple independent flip-flops (first and second flip-flops) that operate in parallel. Each flip-flop processes the phase comparison independently, allowing the system to achieve reliable metastable phenomenon detection without requiring excessive delay time, thus maintaining high operation frequency.
Solution Approach 2:
The patent introduces a coincidence detection mechanism as an intermediary between the flip-flops and the final output. The coincidence detection circuit combines the outputs of multiple flip-flops to generate the final phase comparison result, enabling the system to tolerate shorter delay times while maintaining reliability through statistical probability.
2Productivity
If delay time is reduced for high-frequency operation, then operation frequency is improved, but reliability deteriorates due to increased metastable phenomenon occurrence
Solution Approach 1:
The patent segments the phase comparison function across multiple flip-flops operating in parallel. By distributing the comparison task, each flip-flop can use minimal delay time while the collective output through coincidence detection maintains high reliability, enabling high-frequency operation without sacrificing error prevention.
Solution Approach 2:
The patent changes the operational parameters by using multiple flip-flops with different timing characteristics and combining their outputs through coincidence detection. This parameter change allows the system to achieve both short delay time (for high frequency) and high reliability simultaneously.
3Productivity
If multiple flip-flops are used to reduce delay time, then operation frequency is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple flip-flop outputs through a coincidence detection circuit that combines their signals to generate the final phase comparison result. This merging approach allows the use of multiple simple flip-flops rather than one complex high-speed flip-flop, achieving high frequency operation with manageable circuit complexity.
Solution Approach 2:
The patent makes each flip-flop serve multiple functions: phase sampling, metastable phenomenon detection, and contribution to the final comparison result. This multi-functionality reduces the need for separate circuits, thereby limiting the increase in overall device complexity while maintaining high operation frequency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the delay time required to manage metastable phenomena, allowing for high-frequency operation of DLL circuits with a sufficient operation margin and preventing erroneous operations in connected circuits.
Implementation Method 1
the third and fourth inverter circuits each have a hysteresis characteristic
Implementation Method 2
the first and second inverter circuits are each formed by a current mirror amplifier which inverts an input signal based on a reference voltage generated by a resistive division
Data Source
AI summary
A phase comparing circuit includes a first storage circuit for reading an external clock signal based on a control clock signal; first and second inverters for inverting a signal from the first storage circuit based respectively on first and second threshold levels; third and fourth inverters for inverting respective signals output from the first and second inverters; a delay circuit for delaying the control clock signal by a specific time; a coincidence control circuit for setting the delayed control clock signal to be active when the signals from the third and fourth inverters coincide with each other, and setting it to be inactive when the signals from the third and fourth inverters do not coincide with each other; and a second storage circuit for reading a signal output form the first storage circuit when the delayed control clock signal is active, and outputting the read signal as the control signal.