Phase Controlled Codec Block Scan for Low Power Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current scan chain testing methods face challenges in reducing power consumption during testing, which limits the frequency and efficiency of scan data application, leading to increased test and application times, and higher power dissipation in electronic devices like integrated circuits.
Innovation Solution
The implementation of a low power scan architecture that divides scan chains into segments, using odd and even clocks to phase-shift test vector data, allowing for increased clock frequencies while minimizing power consumption by only activating one segment at a time, and employing dual codecs to manage and compress test data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan chains are operated at high clock frequencies to reduce test time, then productivity is improved, but power consumption increases
Solution Approach 1:
The scan chains are divided into multiple segments, where each segment can be independently clocked. This segmentation allows the test system to activate only the necessary segments at high frequencies while keeping other segments inactive, thereby maintaining high test efficiency for critical paths while reducing overall power consumption.
Solution Approach 2:
The patent implements dynamic clocking where different segments of scan chains can operate at different clock frequencies simultaneously. Critical segments requiring fast testing can run at high frequencies while non-critical segments operate at lower frequencies or remain idle, optimizing the balance between test productivity and power consumption.
2Use of energy by moving object
If scan chains are divided into segments with phase shifting to reduce power consumption, then power is reduced, but device complexity increases
Solution Approach 1:
Multiple scan chain segments are merged into a unified scan architecture that shares common control logic, multiplexers, and compression resources. This merging approach reduces the overall complexity increase that would result from complete segmentation, while still enabling selective phase-shifting and independent clocking of segments.
Solution Approach 2:
The patent employs universal control structures and multiplexers that can route test data to multiple segments and manage phase-shifting operations. These multi-functional components reduce the need for dedicated control logic for each segment, thereby limiting the increase in device complexity while maintaining the power-saving benefits of segmentation.
3Use of energy by moving object
If dual codecs are used to manage segmented scan chains, then power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent uses duplicate (coded) compression resources for different scan chain segments. By having multiple codecs that can be selectively activated, the system reduces power consumption during testing while the codecs themselves are standard components that can be manufactured using conventional processes, limiting the impact on manufacturing complexity.
Data Source
AI summary
A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.