Phase Correction Circuit for Real-Time Clock-Strobe Alignment
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Solution Overview
Problem
Existing semiconductor circuits fail to compensate for the skew between clock and data strobe signals during normal operation, particularly at higher frequencies, leading to difficulties in satisfying the tDQSS specification due to variations in PVT (process, voltage, or temperature) and lack of real-time correction methods.
Innovation Solution
A phase correction circuit that detects the phase difference between clock and data strobe signals, adjusts the delay time of the data strobe signal, and generates a corrected signal, using a delay unit, delay lines, a phase detector, and a shift register to ensure real-time alignment and compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation speed (frequency of clock signal) is increased, then productivity is improved, but the difficulty of satisfying tDQSS specification worsens due to skew between clock and data strobe signals
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller outputs clock and data strobe signals to the memory, the memory samples the clock signal at the rising edge of the data strobe signal, feeds back the sampling results through a DQ pad, and the memory controller adjusts the delay of the data strobe signal based on this feedback until the sampling result becomes '1'. This closed-loop feedback system enables real-time compensation for skew between clock and data strobe signals, allowing the system to maintain tDQSS specification satisfaction even at higher operation speeds.
Solution Approach 2:
The patent applies dynamics by making the delay of the data strobe signal adjustable rather than fixed. The memory controller dynamically adjusts the delay time of the data strobe signal based on the feedback from the memory's sampling results, enabling the system to adapt to varying skew conditions that occur at different operation speeds and PVT variations, thus maintaining reliable operation.
2Device complexity
If write leveling is performed only in the initial step, then device complexity is reduced, but the ability to compensate for skew during normal operation is lost
Solution Approach 1:
The patent implements continuous useful action by performing write leveling not only in the initial step but also continuously during normal operation. The memory controller continuously monitors the sampling results and adjusts the data strobe signal delay in real-time, ensuring that skew compensation is an ongoing process rather than a one-time initialization. This continuous adjustment maintains optimal timing alignment throughout the memory's operational lifetime despite PVT variations.
3Manufacturing precision
If the delay of data strobe signal is adjusted based on sampling results, then manufacturing precision is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent applies universality by using the existing DQ pad, which is already part of the memory interface for data transmission, to also serve as a feedback path for conveying sampling results to the memory controller. This multi-functional use of the DQ pad eliminates the need for separate dedicated feedback channels, reducing the overall device complexity while still achieving precise timing alignment through delay adjustment.
Data Source
AI summary
Various exemplary embodiments of a phase correction circuit are disclosed. In one exemplary embodiment, the phase correction circuit may include a delay unit configured to delay a clock signal by a predetermined delay time and generate a delay clock signal, a delay line configured to delay a data strobe signal by a variable delay time in response to a delay control signal and generate a corrected data strobe signal, a phase detector configured to detect a phase difference between the delay clock signal and the corrected data strobe signal and generate a phase detection signal, and a shift register configured to generate the delay control signal in response to the phase detection signal.