Distributed Phase-Correction Circuit for Delay-Line Jitter Reduction
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Solution Overview
Problem
Existing delay-locked loops (DLLs) amplify input jitter, leading to wider phase windows and difficulties in synchronizing data transfers at high data rates, due to the accumulation of jitter through variable delay lines and inadequate filtering, resulting in start-up and locking issues.
Innovation Solution
A distributed phase-correction circuit with cascaded phase-alignment elements in two delay lines that use local feedback to successively correct the phase of input signals, averaging edge delays to reduce jitter without separate feedback loops for duty-cycle and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a variable delay line is used to adjust clock phase, then phase alignment capability is improved, but jitter accumulates and amplifies through each stage
Solution Approach 1:
The delay line is segmented into multiple identical stages, each contributing a fixed delay. This segmentation allows the system to achieve variable phase alignment by selecting different numbers of stages while maintaining consistent jitter characteristics across all stages, preventing cumulative jitter amplification.
Solution Approach 2:
The invention changes the delay parameter in discrete, identical increments across multiple stages rather than using a continuous variable delay mechanism. This parameter quantization ensures that each stage contributes equally to the total delay while maintaining uniform jitter characteristics, avoiding the jitter amplification problem of continuous variable delay lines.
2Reliability
If loop bandwidth is reduced to lower jitter peaking, then jitter peaking is reduced, but responsiveness to reference clock changes deteriorates
Solution Approach 1:
The system dynamically switches between different fixed delay stages based on the required phase adjustment, rather than using a continuous variable delay with low bandwidth feedback. This dynamic switching allows rapid response to reference clock changes while maintaining low jitter peaking, as each fixed stage contributes uniformly to the delay without amplifying jitter.
3Reliability
If multiple feedback loops are added to correct duty-cycle and temperature variations, then correction capability is improved, but device complexity increases
Solution Approach 1:
Each identical delay stage is designed to perform multiple functions simultaneously: it provides the primary delay function, contributes to duty-cycle correction through its symmetric structure, and compensates for temperature variations via matched device pairs. This multi-functionality eliminates the need for separate feedback loops, reducing overall system complexity while maintaining comprehensive correction capability.
Solution Approach 2:
The invention merges the functions of duty-cycle correction, temperature compensation, and phase alignment into a single integrated delay line structure. By combining these functions in the basic delay stage design itself, the system achieves comprehensive correction without requiring additional separate feedback loops, thereby reducing device complexity.
Data Source
AI summary
A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line.