Phase-Accumulation DAC Using Time Conversion for Low-Power Scaling
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs) face challenges in reducing power consumption and physical size due to the need for large analog components and high voltage supplies, especially at low voltage technologies where voltage headroom is limited.
Innovation Solution
A phase accumulation digital-to-analog converter design utilizing digital-to-time converters, phase-to-time logic, and time-to-voltage converters with minimal analog components, operating on a single 0.8V supply, featuring capacitors with weighted capacitance values and a charger with switches to minimize power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional current-steering architecture is used to achieve high-speed operation with sufficient linearity, then speed and linearity are improved, but power consumption and area increase with a power of 2 for every extra bit of resolution
Solution Approach 1:
The patent replaces the conventional current-steering architecture with a digital-to-time converter (DTC) approach. Instead of using current mirrors and steering networks that require large analog components, the invention uses digital delay elements and phase accumulation to achieve the same DAC function. This substitution of the fundamental conversion mechanism dramatically reduces power consumption and area while maintaining high-speed operation capability.
Solution Approach 2:
The invention changes the fundamental parameter being converted from direct current amplitude (conventional DAC) to time delay/phase (DTC approach). By converting digital words to time delays and then to analog voltage through a time-to-voltage converter, the system achieves high resolution without the exponential scaling of power and area required by conventional current-steering architectures.
2Area of stationary object
If analog components are reduced to minimize area and power consumption, then area and power are improved, but maintaining high linearity and resolution becomes difficult
Solution Approach 1:
The patent replaces precision analog components (current mirrors, resistors, capacitors) with digital logic elements (delay elements, flip-flops, multiplexers) for the DTC function. This substitution allows high linearity to be achieved through digital logic precision rather than analog component matching, significantly reducing area while maintaining or improving linearity performance.
3Manufacturing precision
If voltage headroom is increased to allow cascading transistors for high linearity, then linearity is improved, but in low voltage technologies (0.8V supply) voltage headroom becomes insufficient
Solution Approach 1:
The patent replaces the transistor cascading approach (which requires voltage headroom) with a digital logic-based DTC architecture. The delay elements, flip-flops, and multiplexers used in the DTC can operate efficiently at low voltages (0.8V), eliminating the need for high voltage supplies while achieving high linearity through digital logic precision.
4Measurement precision
If resolution is increased in conventional DACs to improve precision, then measurement precision is improved, but power consumption and area increase with a power of 2
Solution Approach 1:
The invention changes the conversion parameter from direct current amplitude to time delay. The DTC uses N-bit digital words to control N delay elements, where each delay element contributes a weighted delay proportional to its bit significance. This approach achieves high resolution (e.g., 10-bit or 12-bit) with area that scales linearly with N rather than exponentially, as the delay elements can be implemented using simple digital logic circuits.
Solution Approach 2:
The patent segments the resolution into individual delay elements, each controlled by a separate bit of the digital input word. Each delay element processes one bit and contributes a proportional delay, allowing the total delay to represent the full digital word value. This segmentation enables high resolution to be achieved through parallel processing of multiple bits rather than requiring exponentially increasing analog component precision.
Data Source
AI summary
A phase accumulation digital-to-analog converter (DAC) is provided. A digital-to-time converter (DTC), including a reference clock chain with N number of series connected delay elements, accepts a clock signal with a leading clock edge and supplies a set signal representing a first delay of the leading clock edge. A data clock chain including N number of series connected accumulators, accepts the clock signal with the leading clock edge, accepts a binary coded digital word, and supplies a reset signal representing a second delay of the leading clock edge, responsive to the digital word. A phase-to-time logic (PTL) receives the set and reset signals and supplies a DTC output signal representing the difference in delay between the set and reset signals. A time-to-voltage converter (TVC) charges a load capacitor every clock period in response to the DTC output signal to supply an analog output signal.