Phase-Delay ADC Circuit Using Gated Ring Oscillator Counting
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Solution Overview
Problem
Conventional dual-slope analog-to-digital converters (ADCs) face a trade-off between conversion time and resolution, and clocking using rising and/or falling edges limits conversion speed, making it difficult to achieve high-speed conversion with satisfactory noise performance at both low and high bit resolutions.
Innovation Solution
The implementation of phase delay counting using a gated ring oscillator (GRO) in ADC circuitry, which allows for faster conversion by digitizing integration periods and using phase states to calculate analog input values, enabling higher resolution and speed while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional dual-slope ADCs use rising and/or falling edges of a clock signal for counting, then the conversion process is simpler to implement, but the conversion speed is inherently limited
Solution Approach 1:
The patent replaces the mechanical clock edge counting system with a phase delay counting system. Instead of using rising/falling edges of a clock signal, the invention uses phase nodes from a ring oscillator to count integration periods. This substitution enables faster conversion speeds while maintaining implementation feasibility through the phase delay counting mechanism.
Solution Approach 2:
The patent changes the fundamental parameter used for counting from clock edge transitions to phase node delays. By using multiple phase nodes (e.g., 10 phase nodes) from the ring oscillator, the system achieves higher conversion speeds since each phase node represents a smaller time increment, allowing more precise and faster measurement of integration periods.
2Measurement precision
If dual-slope ADCs increase bit resolution, then measurement precision improves, but conversion time increases
Solution Approach 1:
The patent segments the counting process into multiple phase nodes. Instead of using a single clock edge to count the entire integration period, the system divides the period into multiple phase-delays (e.g., 10 phase nodes). This segmentation allows the ADC to achieve high bit resolution by counting through multiple finer-grained phase increments rather than relying on a single coarse clock edge, thereby reducing total conversion time while maintaining precision.
Solution Approach 2:
The patent employs periodic phase nodes from a ring oscillator to count integration periods. The ring oscillator generates a series of periodic phase nodes that traverse through multiple delay stages. By using these periodic phase nodes instead of a single clock edge, the system can rapidly count through multiple integration periods, achieving high resolution conversions in shorter timeframes through repeated periodic measurements.
3Productivity
If dual-slope ADCs achieve high-speed conversion, then productivity improves, but noise performance deteriorates
Solution Approach 1:
The patent introduces phase nodes from a ring oscillator as an intermediary between the integration process and the counting mechanism. These phase nodes serve as a mediator that enables fast counting of integration periods without directly coupling the high-speed switching to the integrator input. The phase delay mechanism acts as a buffer that allows rapid measurement while maintaining stable integration conditions, thereby achieving high conversion speeds without degrading noise performance.
Data Source
AI summary
An analog-to-digital converter may include an integrator, a gated ring oscillator, a coarse counter, a phase state register, a counter register, and logic circuitry. The gated ring oscillator may output a phase state signal continuously to the phase state register. The phase state signal includes multiple phase nodes, each of which is created by transmitting a signal through a number of delay stages. One of the phase nodes may be provided to the coarse counter. The phase state register and counter register may store the most current corresponding phase state and coarse counter outputs, respectively. A control signal corresponding to an analog image input signal may control the output of stored phase states and stored coarse counter outputs to the logic circuitry. The logic circuitry may generate a digital version of the analog image input signal based on the outputs of the phase state and counter registers.