Dynamic Phase Delay Compensation for Emulator Clock Synchronization
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Solution Overview
Problem
The communication speed between digital signal processor (DSP) evaluation boards and emulators is limited by delays in the digital circuit, with conventional techniques either failing to adjust skew or requiring additional pins, leading to suboptimal operating frequencies.
Innovation Solution
A method and apparatus for dynamically adjusting a data clock in a digital circuit by applying a reference clock signal, sampling delayed return data, comparing it to an expected signal, and adjusting the sample clock delay until equality is achieved, thereby synchronizing communication between the digital circuit and the emulator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to improve communication speed, then the operating frequency improves, but communication reliability deteriorates due to delay-induced bit errors
Solution Approach 1:
The patent changes the delay parameter of the clock signal dynamically. A delay lock loop circuit adjusts the delay of the sample clock signal to match the delay of the data signal path, allowing the system to operate at higher frequencies while maintaining synchronization and reliability. The delay parameter is continuously monitored and adjusted to compensate for variations in the data path delay.
2Reliability
If a user-specified clock is used to account for timing delays, then communication reliability improves, but device complexity increases due to additional pins
Solution Approach 1:
The system performs self-synchronization by automatically measuring the delay in its own data path and adjusting its clock signal accordingly. The delay lock loop circuit monitors the timing relationship between data signals and clock signals, and autonomously adjusts the clock delay to achieve optimal synchronization without requiring external intervention or additional hardware pins.
3Measurement precision
If the sampling period is decreased to find the failure point, then bit error detection improves, but productivity decreases due to reduced operating frequency
Solution Approach 1:
The patent implements a feedback mechanism where the system continuously monitors for bit errors and uses this information to adjust the clock delay. The delay lock loop detects timing errors in the returned data and feeds this information back to adjust the sample clock delay, maintaining optimal synchronization without requiring reduced operating frequencies or extensive error testing.
Data Source
AI summary
An apparatus, method, and article to dynamically adjust a data signal using a regenerated clock signal in an emulator to increase communication speed between the emulator and the evaluation board is disclosed. In one embodiment, this is achieved by applying a reference clock signal at a predetermined frequency to a digital circuit. A delayed return data signal is then sampled from the digital circuit. The sampled delayed return data signal is then compared to an expected return data signal. The delayed return data signal is then adjusted as a function of the comparison to increase the communication speed between the emulator and the evaluation board.