Phase Difference Quantization Circuit With Replica Delay Calibration

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The delay value ratios in phase difference quantization circuits tend to deviate due to variations in PVT (process, voltage, and temperature), leading to inaccurate generation of binary codes representing phase differences between signals.

Innovation Solution

A delay value control circuit is introduced, which includes replica delay units and a delay control unit to compare phases and adjust delay values, maintaining constant ratios between delay units through calibration modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If delay units are used in phase difference quantization circuits, then phase difference measurement is enabled, but delay value ratios deviate due to PVT variations

Engineering Contradiction:
Improvephase difference measurement accuracyVSAvoiddelay value ratio stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the delay control unit continuously monitors the delay values of multiple delay units and adjusts their delay values to maintain constant ratios. The control unit receives feedback about PVT variations and compensates for them by dynamically adjusting delay values, ensuring that the ratio relationships between delay units remain stable despite environmental changes.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the delay values of delay units dynamically based on detected PVT variations. The delay control unit modifies the delay parameters of individual delay units to compensate for ratio deviations caused by process, voltage, and temperature changes. This parameter adjustment ensures that the delay value ratios remain constant despite external condition variations.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If delay value ratios are maintained constant through control circuits, then measurement accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvebinary code accuracyVSAvoidcontrol circuit structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent uses a replica delay unit that copies the structure and characteristics of the actual delay units. The delay control unit compares the delay value of the replica unit with the expected value and uses this comparison to adjust the delay values of the actual delay units. This copying approach simplifies the control mechanism by providing a reference model for comparison and adjustment.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The delay control unit automatically detects and corrects delay value ratio deviations without requiring external calibration or manual adjustment. The system performs self-diagnosis and self-correction by monitoring its own delay units and dynamically adjusting their parameters to maintain constant ratios, thereby eliminating the need for complex external calibration equipment or procedures.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8836373B2Phase difference quantization circuit, delay value control circuit thereof, and delay circuit
Publication Date: 2014.09.16 SK HYNIX INC
  • US8836373B2 patent drawing
  • US8836373B2 patent drawing
  • US8836373B2 patent drawing

AI summary

A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2≦A≦N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A−1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.