Phase Prediction Demodulator Circuit for HART Clock Regeneration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
HART protocol demodulators face challenges in accurate data capture clock regeneration due to lack of phase and slope data, leading to demodulation failures and high error rates, especially in noisy and varying waveform conditions.
Innovation Solution
A phase prediction demodulator circuit that adjusts the data capture clock based on detected pulse width changes, predicting transitions from data1 to data0 and dynamically generating the capture clock to improve data capture accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional HART protocol demodulators are used without phase prediction, then the device complexity is reduced, but the measurement precision of data capture clock regeneration deteriorates leading to demodulation failures
Solution Approach 1:
The patent applies preliminary action by measuring the pulse width of the received signal before generating the data capture clock. The counter circuit measures the pulse width of the current bit, and based on this measurement, the system predicts and adjusts the phase of the data capture clock for the next bit. This preliminary measurement enables accurate clock regeneration without requiring complex synchronous sampling circuits, thereby improving measurement precision while keeping device complexity manageable.
2Reliability
If phase prediction is implemented to improve data capture accuracy, then the reliability of demodulation is improved, but the device complexity increases due to additional counter and control circuitry
Solution Approach 1:
The patent applies self-service by using the received signal itself to generate the data capture clock. The counter circuit measures the pulse width of the received signal, and this measurement directly controls the phase adjustment of the data capture clock. The system serves itself by extracting timing information from the signal being processed, eliminating the need for external synchronization or complex control circuits, thereby improving reliability without significantly increasing device complexity.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the phase of the data capture clock based on the measured pulse width. The counter circuit measures the pulse width parameter, and this parameter is used to modify the phase parameter of the data capture clock. This dynamic parameter adjustment enables the system to adapt to signal variations and improve demodulation reliability while using simple circuitry.
3Measurement precision
If ADC-based solutions are used for demodulation, then the measurement precision is improved, but the use of energy and device size increase significantly
Solution Approach 1:
The patent applies this principle by replacing expensive, high-power ADC-based demodulation with a simpler, low-power counter-based approach. Instead of using complex analog-to-digital conversion circuitry that consumes significant power, the system uses simple counter circuits to measure pulse width and generate timing signals. This disposable-like simplicity in the demodulation approach achieves adequate measurement precision while dramatically reducing power consumption and device size.
Data Source
AI summary
An example apparatus includes: an input adapted to receive a signal modulated with data, counter circuitry coupled to the input and operable to determine a first count value in response to a first period between a first rising edge of the signal and a second rising edge of the signal, the first rising edge indicative of a start bit of the data, and determine a second count value based on a second period between a first falling edge of the signal and a second falling edge of the signal, data capture clock circuitry coupled to the counter circuitry and operable to generate a data capture clock based on the first count value in response to the second count value satisfying a threshold, and demodulator circuitry coupled to the counter circuitry and the data capture clock circuitry, the demodulator circuitry operable to generate a demodulated signal based on the data capture clock.