Phase Detection Circuit for Division Clock Signal Alignment
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Solution Overview
Problem
Semiconductor devices operating with division clock signals face challenges in synchronizing phases of clock signals, leading to inefficiencies in data processing and operation speed, particularly in modes like 8-bank and 16-bank operations where precise phase alignment is crucial.
Innovation Solution
Incorporating a phase difference detection circuit and internal circuitry that generates and compares phase difference signals to recognize and align phases of division clock signals and internal division clock signals, allowing for domain crossing operations to adjust command pulses and selection clock signals accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a division clock signal is used to improve operation speed, then the operation speed of the semiconductor device is improved, but phase misalignment between clock signals occurs leading to synchronization issues
Solution Approach 1:
The patent implements a phase difference detection circuit that continuously monitors the phase relationship between the division clock signal and reference clock signal, generating detection signals that feed back to a phase adjustment circuit. This closed-loop feedback mechanism automatically corrects phase misalignment, ensuring reliable synchronization while maintaining high operation speed enabled by the division clock signal.
Solution Approach 2:
The patent introduces a phase adjustment circuit as an intermediary component between the division clock signal generator and the clock signal users. This intermediary circuit receives the division clock signal, adjusts its phase based on detection signals, and outputs a phase-corrected clock signal, thereby resolving the phase misalignment issue without affecting the high-speed operation benefit.
2Reliability
If phase detection and adjustment circuits are added to align clock phases, then phase alignment is improved, but device complexity increases
Solution Approach 1:
The patent merges the phase difference detection function and phase adjustment function into an integrated phase synchronization circuit module. By combining these functions that were previously separate, the design achieves the required phase alignment capability while minimizing the increase in device complexity through functional integration and shared circuit resources.
Solution Approach 2:
The phase detection and adjustment circuits are designed with multi-functionality, serving both phase synchronization purposes and acting as part of the overall clock distribution system. The same circuit structures are reused across different bank groups and operation modes, reducing overall device complexity through universal design principles.
3Productivity
If multiple bank groups are operated simultaneously to increase productivity, then data processing capability is improved, but synchronization difficulty increases
Solution Approach 1:
The patent segments the clock synchronization system into independent phase detection and adjustment units for each bank group. Each bank group has its own phase difference detection circuit and phase adjustment circuit, allowing simultaneous operation of multiple bank groups with independent phase control. This segmentation enables high productivity through parallel operation while managing synchronization complexity through modular design.
Solution Approach 2:
The patent implements phase detection and adjustment for each bank group independently, which may seem like excessive action, but actually simplifies the overall synchronization control by localizing the complexity to manageable units. This partial implementation approach allows the system to handle multiple bank groups simultaneously without requiring complex global synchronization control.
Data Source
AI summary
A semiconductor device includes a phase difference detection circuit and an internal circuit. The phase difference detection circuit generates first and second phase difference detection signals by comparing a phase of a phase detection clock signal, generated from a command/address signal in synchronization with a clock signal, with phases of a division clock signal and an internal division clock signal that are generated by dividing a frequency of a data clock signal according to an operation mode. The internal circuit recognizes the phases of the division clock signal and the internal division clock signal according to a logic level combination of the first and second phase difference detection signals.