Phase Difference Detection Circuit for Semiconductor Write Leveling
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Solution Overview
Problem
Semiconductor devices face challenges in ensuring the reliability of write leveling operations due to the difficulty in accurately adjusting the phase difference between clock and strobe signals with different frequencies, which affects data input and output synchronization.
Innovation Solution
A semiconductor device with a phase difference detection circuit that generates a detection signal synchronized with the clock, a control signal generation circuit to store and output this signal, and a phase difference adjustment circuit to adjust the phase of the clock and strobe signals based on the detection, ensuring reliable write leveling operations by synchronizing data input and output with the internal strobe signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the phase difference between clock and strobe signals is adjusted for write leveling, then data input and output synchronization is improved, but the complexity of phase detection and adjustment circuits increases
Solution Approach 1:
The patent introduces a write leveling control circuit as an intermediary component that mediates between the clock signal and strobe signal. This circuit generates detection signals by comparing phases and produces control signals to adjust the strobe signal phase, thereby simplifying the overall system architecture while achieving reliable write leveling operations
Solution Approach 2:
The patent implements a feedback mechanism where the write leveling control circuit continuously monitors the phase difference between clock and strobe signals, generates detection signals based on phase comparisons, and adjusts the strobe signal phase accordingly. This closed-loop feedback system ensures accurate synchronization while maintaining manageable circuit complexity through systematic control
2Measurement precision
If the detection signal is generated at the logic level of the strobe signal in synchronization with the clock, then measurement precision of phase difference is improved, but the difficulty of detecting and measuring increases
Solution Approach 1:
The patent changes the parameter of detection signal generation by producing the detection signal at the logic level of the strobe signal rather than directly comparing raw signals. This parameter transformation simplifies the detection process while maintaining high measurement precision, as the logic level comparison is easier to implement and less prone to noise interference
Data Source
AI summary
A semiconductor device includes a phase difference detection circuit configured to generate a detection signal by detecting a phase difference of a clock and a strobe signal, the detection signal being generated at a logic level of the strobe signal in synchronization with the clock, and configured to generate a write clock by delaying the strobe signal. The semiconductor device also includes a control signal generation circuit configured to store the detection signal, in synchronization with the write clock, and configured to output the stored detection signal as a control signal.