Phase Detection Circuit for Stable Multi-Phase Clock Synchronization

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Solution Overview

Problem

Semiconductor apparatuses face challenges in generating internal clock signals with constant phase differences due to skews in clock paths, affecting operation reliability.

Innovation Solution

A phase detection circuit comprising an edge trigger circuit, a strobe generation circuit, and a phase detector is used to generate falling and rising clock signals, strobe signals, and phase detection signals, allowing for adjustment of internal clock signal phases to maintain constant phase differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple internal clock signals are generated through different clock paths, then the clock generation circuit can provide multiple phases for operation reliability, but the phase differences among these signals become unstable due to clock path skews

Engineering Contradiction:
Improveoperation reliabilityVSAvoidphase difference consistency
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent employs a feedback mechanism where a phase detector continuously monitors the phase differences between internal clock signals generated through different clock paths. Based on the detection results, the system adjusts the clock paths to compensate for skews, ensuring stable phase differences. This closed-loop feedback control resolves the contradiction by dynamically correcting phase variations while maintaining multiple clock paths for operational reliability.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces a phase detector and adjustment mechanism as an intermediary component between the multiple clock paths. This intermediary monitors and regulates the phase relationships among clock signals, preventing direct interference from path skews. By inserting this mediating control layer, the system maintains stable phase differences despite using multiple independent clock paths for reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the clock paths are made more complex to generate multiple phases, then more internal clock signals can be produced, but the phase stability deteriorates due to increased skew variations

Engineering Contradiction:
Improvemulti-phase generation capabilityVSAvoidphase relationship stability
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The phase detector continuously monitors phase relationships among multiple internal clock signals and feeds this information back to adjustment circuits. This feedback mechanism dynamically compensates for skew variations introduced by complex clock paths, maintaining stable phase relationships while enabling versatile multi-phase clock generation for different operational modes.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent implements dynamic adjustment mechanisms that adaptively compensate for phase skews in real-time. Rather than using fixed rigid clock paths, the system employs adjustable delay elements and phase shifters that can dynamically modify clock signal timing. This dynamic approach maintains phase stability while allowing the complex clock distribution network to serve multiple functional requirements.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11513553B2Phase detection circuit, clock generation circuit and semiconductor apparatus using the phase detection circuit
Publication Date: 2022.11.29 SK HYNIX INC
  • US11513553B2 patent drawing
  • US11513553B2 patent drawing
  • US11513553B2 patent drawing

AI summary

A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.