Phase Detection Circuit to Prevent Harmonic Locking
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Solution Overview
Problem
Existing phase detection circuits in semiconductor apparatuses face challenges in accurately synchronizing clock signals, leading to issues like harmonic locking, which affects the precision of clock signal adjustment and stability in computer systems.
Innovation Solution
A phase detection circuit comprising a clock divider, unit delay, first and second phase detectors, and an initialization signal generator, which compares the phases of input and divided clock signals to generate detection signals and adjust the delay amount of the output clock signal, thereby addressing synchronization challenges and preventing harmonic locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional phase detection circuit is used to synchronize clock signals, then the circuit can detect phase differences, but it suffers from harmonic locking which reduces measurement precision and stability
Solution Approach 1:
The phase detection function is divided into two separate detectors: a first phase detector for initial phase detection and a second phase detector for refined phase detection. This segmentation allows the system to avoid harmonic locking by transitioning from one detection mode to another, thereby improving both measurement precision and reliability
Solution Approach 2:
The first phase detector performs preliminary phase detection to establish initial synchronization before the second phase detector takes over for precise phase measurement. This preliminary action prevents harmonic locking from affecting the final measurement precision
2Measurement precision
If the phase detection circuit uses multiple detection stages to improve precision, then phase detection accuracy improves, but the device complexity increases
Solution Approach 1:
The detection circuit is segmented into two functional stages with distinct purposes: initial detection and refined detection. This segmentation achieves high precision without requiring a completely complex redesign, as each stage has a simplified, specialized function
Solution Approach 2:
Both phase detectors and the clock divider share a common initialization mechanism through the initialization signal generator. This merging of initialization resources reduces overall circuit complexity while maintaining the benefits of multi-stage detection
3Productivity
If the clock divider is continuously operated to maintain clock signal division, then clock signal availability is maintained, but initialization errors can propagate and reduce reliability
Solution Approach 1:
The clock divider operates in periodic cycles: during normal operation it continuously divides the clock signal to maintain availability, and during initialization phases it is controlled by the initialization signal to reset and eliminate errors. This periodic initialization ensures reliability without sacrificing continuous clock availability
Solution Approach 2:
The initialization signal generator uses feedback from the phase detection process to determine when initialization is needed. When phase detection indicates misalignment or potential initialization errors, the system triggers re-initialization of the clock divider, thereby maintaining reliability while keeping the divider operational during normal phases
Data Source
AI summary
A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.