Phase Detection Circuit for Stable Multi-Phase Internal Clocks

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Solution Overview

Problem

Semiconductor apparatuses face challenges in generating internal clock signals with constant phase differences due to skews in clock paths, affecting operation reliability.

Innovation Solution

A phase detection circuit comprising an edge trigger circuit, a strobe generation circuit, and a phase detector is used to generate falling and rising clock signals, strobe signals, and phase detection signals, allowing for adjustment of internal clock signal phases to maintain constant phase differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If internal clock signals are generated through different clock paths, then multiple internal clock signals with different phases can be produced, but the phase differences among these signals become non-constant due to clock path skews

Engineering Contradiction:
Improvegeneration of multiple internal clock signals with different phasesVSAvoidconstant phase differences among internal clock signals
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent employs a phase detection circuit that continuously monitors the phase differences among internal clock signals generated through different clock paths. The detection results are fed back to a delay adjustment circuit, which dynamically adjusts the delay amounts of individual clock paths to compensate for skews and maintain constant phase differences, thereby resolving the contradiction between generating multiple phase-diverse clock signals and maintaining their phase relationship stability

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces dynamic delay adjustment mechanisms in each clock path, allowing the delay amounts to be continuously tuned based on detected phase deviations. This dynamic adjustment capability enables the system to adapt to varying conditions and maintain constant phase differences among multiple internal clock signals despite variations in clock path characteristics

Inventive Principle:
Principle #15Dynamics

2Reliability

If delay adjustment is performed on each clock path to maintain constant phase differences, then operation reliability is improved, but the device complexity increases due to additional control circuits

Engineering Contradiction:
Improveconstant phase differences among internal clock signalsVSAvoidcontrol circuits for delay adjustment
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent designs a universal phase detection and control architecture that can be applied to multiple clock paths simultaneously. The phase detection circuit and delay adjustment mechanisms serve multiple functions: detecting phase differences, determining skew amounts, and adjusting delays across different clock paths, thereby reducing the need for separate control circuits for each path and mitigating the increase in device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11907009B2Phase detection circuit, clock generation circuit and semiconductor apparatus using the phase detection circuit
Publication Date: 2024.02.20 SK HYNIX INC
  • US11907009B2 patent drawing
  • US11907009B2 patent drawing
  • US11907009B2 patent drawing

AI summary

A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.