Phase Detector Switching for Multi-Rate Clock Data Recovery
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Solution Overview
Problem
Existing clock data recovery apparatuses face challenges in adapting to multiple transmission rates, leading to increased jittering and hardware costs due to the use of frequency dividers and multiplexers, which affect signal quality and performance.
Innovation Solution
A clock data recovery apparatus with a phase detector that includes a first sampling circuit, a frequency dividing circuit, and a selecting circuit, allowing for selective output of sample results based on the transmission rate, reducing jittering and hardware costs by using the original clock signal for higher transmission rates and frequency divided signals for lower rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If frequency divider and multiplexer are added to support multiple transmission rates, then adaptability to different communication modes is improved, but device complexity and hardware costs increase
Solution Approach 1:
The phase detector dynamically switches between full-rate and half-rate operating modes based on the transmission rate of the input data signal. The sampling circuits and selection circuit enable the detector to adapt its operation mode in real-time, allowing a single device to handle multiple transmission rates without requiring separate hardware paths for each rate.
Solution Approach 2:
The phase detector is designed with universal functionality to operate in both full-rate and half-rate modes using the same core sampling circuits. The selection circuit chooses between different sampling results based on the operating mode, making the device multi-functional without requiring separate dedicated circuits for each transmission rate.
2Adaptability or versatility
If frequency divider is used to reduce clock frequency for lower transmission rates, then adaptability is improved, but signal quality deteriorates due to increased jittering
Solution Approach 1:
The system dynamically selects the appropriate sampling rate based on the transmission rate of the input signal. When operating at lower transmission rates, the phase detector uses half-rate sampling with appropriately timed clock edges rather than frequency division, thereby maintaining signal quality while adapting to different transmission rates.
Solution Approach 2:
The selection circuit acts as an intermediary that chooses between different sampling results from the same sampling circuits, eliminating the need for frequency division. This intermediary selection mechanism allows the system to adapt to different transmission rates without degrading signal quality through frequency division operations.
3Adaptability or versatility
If VCO frequency range is expanded to cover all transmission rates, then adaptability is improved, but hardware costs increase
Solution Approach 1:
The VCO operates at a fixed frequency range, and the system dynamically adjusts the sampling rate and clock edge selection based on the transmission rate. This dynamic adaptation allows the same VCO to support multiple transmission rates without requiring an expanded frequency range, thereby reducing hardware costs.
Solution Approach 2:
Instead of changing the VCO frequency to adapt to different transmission rates, the system changes other parameters such as the sampling rate and the selection of clock edges used for sampling. This parameter change approach maintains VCO simplicity while achieving adaptability to multiple transmission rates.
Data Source
AI summary
A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.