Low-Power Phase Detector Circuit With Equal Delay Latching
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Solution Overview
Problem
Conventional phase detectors in synchronous integrated circuits face challenges with excessive power consumption and chip space usage due to multiple arbiters and delay lines, and they often introduce hysteresis and phase bias, which can lead to inaccurate phase detection, especially at high clock frequencies.
Innovation Solution
A phase detector circuit with a core phase decision block and two parallel delay lines that delay both input clock signals equally, allowing for immediate latching of phase decisions without the need for excessive delay lines or arbiters, thereby reducing power consumption and eliminating hysteresis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple arbiters and delay lines are used in conventional phase detectors, then phase detection capability is provided, but power consumption and chip space increase excessively
Solution Approach 1:
The patent extracts and eliminates redundant components from the conventional phase detector design. Specifically, it removes unnecessary delay lines and arbiters while retaining the essential phase detection functionality through a simplified circuit architecture that uses only two delay lines and a single arbiter, thereby reducing power consumption while maintaining detection capability
Solution Approach 2:
The patent merges multiple separate components into a more integrated structure. By combining the functions of multiple arbiters and delay lines into a unified circuit design with shared resources, the patent reduces the total component count and power consumption while preserving the phase detection function
2Reliability
If multiple arbiters and delay lines are used in conventional phase detectors, then phase detection capability is provided, but chip space usage increases
Solution Approach 1:
The patent extracts and removes redundant delay lines and arbiters from the conventional design, keeping only the essential two delay lines and one arbiter needed for accurate phase detection, thereby significantly reducing the chip area required
Solution Approach 2:
The patent merges the functions of multiple separate arbiters and delay lines into a compact integrated structure, reducing the overall chip space occupation while maintaining full phase detection functionality
3Reliability
If conventional phase detectors with multiple arbiters are used, then phase detection is provided, but hysteresis and phase bias are introduced leading to inaccurate detection
Solution Approach 1:
The patent removes the source of hysteresis and phase bias by eliminating redundant arbiters and unequal delay lines that cause these measurement errors, resulting in a cleaner phase detection signal with improved accuracy
Solution Approach 2:
The patent changes the delay parameters of the two delay lines to be equal, which eliminates the phase bias and hysteresis effects present in conventional designs with unequal delays, thereby improving measurement precision
4Reliability
If conventional phase detectors are used, then phase detection is provided, but response time is slow due to excessive delays
Solution Approach 1:
The patent removes unnecessary delay elements from the conventional phase detector design, eliminating the excessive delays that slow down the response time while maintaining the essential phase comparison functionality
Solution Approach 2:
The patent enables faster phase detection by skipping through the redundant delay stages present in conventional designs, allowing the phase comparison result to be generated and output more quickly
Data Source
AI summary
A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two clock signals and detects the phase relationship between the two signals by determining which signal was received first. In response, the phase decision circuit generates respective logic signals to reflect the phase relationship determination. The circuit also includes a latch circuit that receives the logic signals from the phase decision circuit and holds the phase relationship determination of the circuit a predetermined time after a predetermined transition of both clock signals have occurred. Methods and systems are also disclosed.