Phase Frequency Detector Circuit for Linear Fractional-N PLL Conversion
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Solution Overview
Problem
Current fractional-N phase-locked loop frequency synthesizers introduce noise into the PLL loop due to the conversion of time differences into charge quantities, degrading phase-noise spectral properties, and there is a lack of highly linear methods to prevent this noise introduction.
Innovation Solution
A phase frequency detector circuit with a charge-pump and voltage-controlled oscillator (VCO) is implemented, featuring Up and Down signals that rise and fall in specific configurations to linearize the conversion of phase differences into charge quantities, ensuring noise-shaping spectral properties are maintained and noise is filtered out.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a ΣΔ modulator is used to modulate the division ratio to obtain fractional values, then the frequency synthesizer can generate frequencies that are not integer multiples of the reference frequency, but noise is introduced into the PLL loop due to the conversion of time differences into charge quantities
Solution Approach 1:
The patent introduces a specialized phase frequency detector as an intermediary component between the ΣΔ modulator and the charge pump. This detector converts phase differences into up/down signals with highly linear conversion characteristics, preventing the noise that would otherwise be introduced during the conversion of time differences into charge quantities. The intermediary detector maintains the noise-shaping spectral properties while enabling fractional-N modulation.
Solution Approach 2:
The patent changes the conversion parameter from general time-difference-to-charge conversion to a highly linear phase-difference-to-up-down-signal conversion. By modifying the conversion characteristics in the phase frequency detector, the system maintains noise-shaping properties while enabling fractional frequency synthesis. The linear conversion ratio is maintained across the operating range, preventing noise degradation.
2Object-generated harmful factors
If a highly linear conversion method from phase difference to charge quantities is implemented, then noise introduction is prevented and phase-noise performance is maintained, but the device complexity increases
Solution Approach 1:
The patent replaces the conventional charge pump mechanism with a phase frequency detector that outputs up/down signals. This substitution eliminates the need for direct charge quantity conversion that introduces noise, while the up/down signals can be processed by existing charge pump circuitry. The detector uses standard logic elements (flip-flops, gates) to achieve highly linear conversion without adding significant complexity.
3Device complexity
If conventional phase frequency detection is used, then the circuit is simple, but the conversion from time differences to charge quantities is not highly linear, degrading phase-noise spectral properties
Solution Approach 1:
The patent implements dynamic signal generation where the up and down signals are generated based on the relative phases of the reference and divided VCO signals. The detector dynamically adjusts the up/down signal transitions to maintain highly linear conversion characteristics across varying operating conditions. This dynamic approach ensures consistent linearity without requiring complex static circuitry.
Data Source
AI summary
A phase frequency detector realizes a highly linear conversion from noise-shaped ΣΔ modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL.