Phase Detector Circuit With Metastability Prevention for Clock Skew
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Solution Overview
Problem
In integrated circuits, the increasing path delay due to narrow wire widths leads to clock skew issues, particularly in double-data-rate static dynamic random access memory (SDRAM), where phase synchronization between internal and external signals is challenging, necessitating complex and costly redesigns of phase-locked loops (PLL) and delay-locked loops (DLL) when process or specification changes occur.
Innovation Solution
A phase detector with a metastable prevention stage is introduced, comprising a phase detection stage and a metastable prevention stage, utilizing standard cells and automated layout tools to generate a stable phase comparison result, avoiding metastable issues and enabling design flexibility across different semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If standard phase detection circuits are used, then the design can be simplified, but metastable issues arise leading to unreliable phase detection results
Solution Approach 1:
The patent introduces a metastability prevention circuit as an intermediary component between the phase detection stage and the output. This intermediary stage processes the phase detection results and eliminates metastable states, thereby maintaining both design simplicity and detection reliability.
Solution Approach 2:
The metastability prevention circuit performs preliminary processing on the phase detection results before they are output. By addressing potential metastable issues in advance, the system ensures reliable phase detection without requiring complex redesigns later.
2Reliability
If full custom design is performed to ensure reliability, then phase detection accuracy improves, but design complexity and redesign costs increase significantly
Solution Approach 1:
The phase detector is segmented into distinct functional stages: a phase detection stage using standard circuits and a metastability prevention stage. This segmentation allows the use of simple standard cells for phase detection while adding reliability through a dedicated prevention stage, avoiding the need for entirely custom designs.
Solution Approach 2:
The metastability prevention circuit serves as a universal solution that can be applied to various phase detection designs. It provides a multi-functional approach by handling both standard phase detection results and metastable conditions, reducing the need for process-specific custom designs.
3Adaptability or versatility
If process changes occur, then new specifications must be met, but full custom redesign is required increasing time and cost
Solution Approach 1:
The metastability prevention circuit provides a universal solution that works across different processes and specifications. When process changes occur, the same prevention circuit architecture can be retained and adapted, avoiding the need for complete custom redesigns and reducing time losses.
Data Source
AI summary
A phase detector, arranged for comparing a phase of a first clock with a phase of a second clock. The phase detector includes a phase detection stage and a metastable prevention stage. The phase detection stage is arranged to receive the first clock and the second clock, and to output a phase comparison result in accordance with the phase of the first clock and the phase of the second clock. The metastable prevention stage is arranged to receive the phase comparison result, and to output a stable phase comparison result in accordance with the phase comparison result.