Digital Phase-Frequency Detector for Near-Lock Synchronization
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Solution Overview
Problem
Traditional digital phase detectors face challenges in accurately indicating the phase difference between local and reference signals when the loop is close to 'lock', making it difficult to achieve precise synchronization in digital phase locked loops.
Innovation Solution
A digital phase-frequency detector comprising an input circuit, output circuit, and reset circuit that determines which input signal was received first during a cycle, generating and outputting intermediate and output signals accordingly, and applying a reset signal to initiate new cycles, utilizing latches, mutex elements, and NOR and NAND gates to manage signal timing and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional digital phase detectors are used, then the circuit is simple, but the measurement precision of phase difference deteriorates when the loop is close to lock
Solution Approach 1:
The phase detection function is segmented into two distinct detection modes: first-edge detection (for large phase differences) and second-edge detection (for small phase differences near lock). The circuit switches between these modes based on the phase difference magnitude, allowing high precision near lock while maintaining simplicity through modular detection paths.
Solution Approach 2:
The detector dynamically switches between different detection mechanisms based on the operating condition. When the phase difference is large, the first detection path is active; when the phase difference is small (near lock), the second detection path takes over. This dynamic adaptation resolves the contradiction by optimizing precision for each operating regime.
2Reliability
If traditional digital phase detectors are used, then the device complexity is low, but the reliability of control signal generation deteriorates when phase difference is small
Solution Approach 1:
The circuit performs preliminary detection using the first detection path for large phase differences, then transitions to the second detection path when approaching lock. This preliminary action ensures that the appropriate detection mechanism is already prepared and active, maintaining reliable control signal generation across all operating conditions.
Solution Approach 2:
The patent introduces an intermediary mechanism (the dual-detection architecture with switching logic) that mediates between the two detection paths. This intermediary structure ensures smooth transition and reliable operation by selecting the appropriate detection path based on phase difference magnitude, improving reliability without excessive complexity.
3Measurement precision
If the phase difference between signals is very small (close to lock), then the synchronization accuracy should be high, but the traditional detector's ability to indicate phase difference deteriorates
Solution Approach 1:
The detector employs different detection qualities for different phase difference ranges. The first detection path is optimized for large phase differences, while the second detection path is specifically optimized for small phase differences near lock. This local quality differentiation ensures high measurement precision and reliable control signal generation in each operating regime.
Solution Approach 2:
The detector changes its operational parameters based on the phase difference magnitude. When the phase difference is small, the circuit switches to the second detection path which uses different timing and comparison parameters optimized for small phase differences. This parameter adaptation maintains high accuracy and reliability across the full operating range.
Data Source
AI summary
Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.