Binary Phase Detector PLL Filtering for High-Bit-Rate Clock Lock
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Solution Overview
Problem
Phase-lock loops (PLLs) face challenges in generating a clock signal from a data stream without a dedicated reference signal, especially at high bit rates, and existing techniques may not effectively lock the oscillator to the input data stream using binary phase detectors in digital techniques.
Innovation Solution
A PLL circuit and method that synthesizes a clock signal from an incoming data stream using a binary phase detector to generate polarity signals indicating phase lead or lag, which are filtered and integrated to control an oscillator, eliminating the need for a separate reference signal and enabling phase locking at high bit rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a binary phase detector is used to generate polarity signals in a digital PLL, then the circuit complexity is reduced and ease of manufacture is improved, but the ability to effectively lock the oscillator to the input data stream at high bit rates deteriorates
Solution Approach 1:
The phase detection function is segmented into multiple independent polarity signal generators, each producing a binary polarity signal indicating phase lead or lag. This segmentation allows the use of simple digital logic elements while maintaining effective phase locking through the combined action of multiple polarity signals.
Solution Approach 2:
Polarity signals are introduced as intermediary elements that mediate between the simple binary phase detection and the oscillator control. These polarity signals, while not directly representing the amount of phase difference, serve as effective mediators to guide the oscillator toward lock through the feedback loop.
2Device complexity
If polarity signals indicating phase lead or lag are generated without representing the amount of phase difference, then the measurement precision of phase difference is reduced, but the device complexity is reduced
Solution Approach 1:
The essential information for phase locking (polarity of phase difference) is extracted from the full phase difference signal. By taking out only the polarity indication and discarding the magnitude information, the system achieves effective phase locking with simpler binary logic while the feedback loop naturally converges to the correct operating point.
Solution Approach 2:
The phase difference parameter is transformed from a continuous magnitude measurement to a discrete polarity indication. This parameter change from analog-like precision to binary states simplifies the device complexity while the feedback mechanism ensures the oscillator converges to the correct phase relationship.
3Reliability
If multiple filtering paths are used for polarity signals, then the phase locking reliability at high bit rates is improved, but the device complexity increases
Solution Approach 1:
The filtering function is segmented into multiple independent paths, each processing polarity signals through separate digital filter circuits. This segmentation allows each filter to operate with simpler logic while the combined output of multiple paths provides robust phase locking capability at high bit rates.
Data Source
AI summary
A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.