Phase Detector Re-Timed Clocking to Avoid Counter Metastability
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Solution Overview
Problem
Metastability issues arise in electronic circuits due to the asynchronous nature of reference and output clocks, leading to incorrect count values when reading counter values, which impede the phase locked loop's acquire and track operations.
Innovation Solution
A phase locked loop generates a re-timed reference clock by comparing the fractional portion of the output clock's cycles with thresholds, selecting appropriate re-timed clocks to read counter values, thereby avoiding metastability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference clock is used to read counter values in an asynchronous clock system, then phase detection operation is enabled, but metastability issues cause incorrect count values to be read
Solution Approach 1:
The patent applies preliminary action by generating a re-timed reference clock in advance that is synchronized to the output clock edges. This re-timed clock is prepared beforehand to ensure proper timing alignment before the actual counter reading operation occurs, preventing metastability issues from the outset
Solution Approach 2:
The patent introduces a re-timed reference clock as an intermediary between the original reference clock and the counter reading operation. This intermediate clock signal serves as a mediator that bridges the asynchronous timing domains, allowing reliable counter value acquisition without direct asynchronous sampling
2Measurement precision
If the reference clock directly samples the counter, then the phase detector operates simply, but metastability causes wrong phase error signals
Solution Approach 1:
The re-timed reference clock is generated in advance with proper phase alignment to the output clock. This preliminary timing preparation ensures that when the counter is sampled, the sampling occurs at optimally timed moments that avoid metastability, thereby ensuring accurate phase error measurement
Solution Approach 2:
The patent changes the timing parameter of the reference clock by generating a re-timed version with adjusted phase relationship relative to the output clock. This parameter modification (clock timing/phase) transforms the sampling operation from metastable to stable, improving measurement precision
Data Source
AI summary
A phase detector includes a counter to generate the integer portion of a number of complete cycles of an output clock at each active edge of a reference clock. A time to digital converter in the phase detector generates the fractional portion of the number of complete cycles of the output clock at each active edge of the reference clock. The sum of the fractional portion and the integer portion is subtracted from an accumulated value obtained by accumulating a pre-determined number to generate an error signal as the output of the phase detector. The counter is read at an active edge of one of two re-timed clocks derived from the reference clock. Each of the two re-timed clocks is generated based on a comparison of the fractional portion with a pair of thresholds. Errors due to metastability in reading the counter are thereby avoided.