Phase Detector Sampling Scheme for Multi-Clock Phase Error Reduction
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Solution Overview
Problem
Phase errors occur when multiple clock signals with phase shifts, such as 90 degrees, are used to sample the same data signal, leading to errors in phase detection in signal processing systems.
Innovation Solution
A phase detector system that includes sampling units and a phase determining module, where a second sampling unit samples a data signal using a first clock signal, and a third sampling unit samples the same signal using the second clock signal, allowing for the generation of a phase detecting result that aligns the sampling edge of the clock signals with the data signal center, reducing phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple clock signals with phase shifts are used to sample the data signal, then the sampling coverage is improved, but phase errors occur between the sampled data
Solution Approach 1:
The patent introduces a phase calibration mechanism that acts as an intermediary between the multiple clock signals and the sampling process. The phase detector detects phase differences between clock signals, and the calibration unit adjusts the sampling timing accordingly, mediating the impact of phase shifts on sampling accuracy.
Solution Approach 2:
The patent dynamically changes the sampling timing parameters based on detected phase differences. The calibration unit modifies the sampling instant to compensate for phase shifts in different clock signals, thereby maintaining accurate phase detection across multiple clock sources.
2Device complexity
If the sampling edge is aligned with the clock signal, then the sampling process is simplified, but phase errors occur due to phase shifts between clock signals
Solution Approach 1:
The patent performs preliminary phase calibration before the actual sampling process. The phase detector and calibration unit pre-adjust the sampling timing based on detected phase differences, so that when sampling occurs, the timing is already optimized to avoid phase errors without complicating the sampling process itself.
Solution Approach 2:
The patent implements a feedback mechanism where the phase detector continuously monitors phase differences between clock signals and feeds this information back to the calibration unit, which then adjusts the sampling timing. This closed-loop feedback ensures accurate phase detection while maintaining a relatively simple sampling process.
Data Source
AI summary
A phase detector includes a first sampling unit, a sampling module and a phase determining module. The first sampling unit is arranged for sampling a first data input signal to generate a first data signal according to a first clock signal. The sampling module includes a second sampling unit and a third sampling unit. The second sampling unit is arranged for sampling a second data input signal to generate a second data signal according to a second clock signal. The third sampling unit is arranged for sampling the second data signal to generate a third data signal according to the first clock signal. The phase determining module is arranged for generating a phase detecting result according to the first data signal and the third data signal.