Phase-to-Digital Converter for Wide-Range ADPLL Timing Detection
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Solution Overview
Problem
Conventional analog phase locked loops (PLLs) face challenges in design and implementation at low power supply voltages and advanced digital processes, such as in 65nm CMOS processes, due to inefficiencies in analog building blocks like operation amplifiers and current mirrors, and require large silicon area, making them expensive and difficult to implement effectively.
Innovation Solution
An all-digital phase locked loop (ADPLL) is developed, utilizing a phase to digital converter (PDC) that converts analog phase information into digital form, enabling fine resolution and high linearity, and supporting wide phase input ranges through edge recycling counters, which reduces power consumption and silicon area, allowing for implementation in deep submicron processes without off-chip components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional analog building blocks (operation amplifiers, current mirrors) are used in advanced CMOS processes like 65nm, then the design becomes difficult and unreliable, but switching to digital building blocks requires new architectures that may increase complexity
Solution Approach 1:
The patent replaces analog building blocks (operation amplifiers, current mirrors) with digital building blocks in the PLL architecture. Specifically, the phase detector uses digital logic to detect phase differences, the charge pump is replaced with a digital counter that increments or decrements based on phase comparison results, and the loop filter is implemented as a digital accumulator. This substitution eliminates the reliability issues of analog circuits in deep submicron processes while maintaining PLL functionality through digital signal processing.
Solution Approach 2:
The patent changes the operating parameters and domain of the PLL from analog to digital. The phase detector operates in the digital domain, producing discrete count values rather than continuous voltage signals. The loop filter processes digital count values through accumulation and averaging, producing digital control words for the voltage-controlled oscillator. This parameter change from continuous analog signals to discrete digital values enables reliable operation in 65nm CMOS while achieving the desired phase locking function.
2Reliability
If analog PLL is implemented with large area filter function, then filtering performance is improved, but silicon area increases making it expensive at 65nm
Solution Approach 1:
The patent replaces the large-area analog filter circuit with a digital filter implemented in the logic domain. The digital filter uses simple digital logic operations (comparators, counters, accumulators) that occupy minimal silicon area compared to the continuous-time analog filter components (capacitors, resistors, op-amps). The filtering function is achieved through digital signal processing algorithms rather than passive analog components, dramatically reducing the required silicon area while maintaining effective noise filtering and phase error correction.
3Use of energy by moving object
If supply voltage is reduced to around 1.1V in 65nm process to reduce power consumption, then power efficiency is improved, but conventional analog building blocks don't work well
Solution Approach 1:
The patent substitutes digital logic circuits for analog building blocks that would otherwise require higher supply voltages to operate reliably. The phase detector, charge pump, and loop filter are all implemented using digital logic that can function correctly at 1.1V supply voltage. Digital logic gates and flip-flops are inherently more robust to voltage scaling than analog circuits, allowing the entire PLL to operate at low voltage with minimal power consumption while maintaining reliable phase detection and control functions.
Data Source
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AI summary
A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.