Phase-to-Digital Converter for Fine and Coarse ADPLL Tracking
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Solution Overview
Problem
Conventional analog phase locked loops (PLLs) face challenges in design and implementation at low power supply voltages, such as 1.1V, due to inefficiencies in analog building blocks like operation amplifiers and current mirrors, and require large silicon area, making them expensive and difficult to implement in advanced CMOS processes like 65nm.
Innovation Solution
An all-digital phase locked loop (ADPLL) is developed, utilizing a phase to digital converter (PDC) that converts analog phase information into digital words, enabling PLL functions in digital circuitry with reduced silicon area and low power consumption, and supports both fine and coarse phase conversions with high linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional analog building blocks (operation amplifiers and current mirrors) are used in phase locked loops, then the PLL can be implemented traditionally, but the design becomes difficult and power consumption increases at low power supply voltages like 1.1V
Solution Approach 1:
The patent replaces analog building blocks (operation amplifiers, current mirrors) with digital building blocks in the phase locked loop. The phase detector, loop filter, and voltage controlled oscillator are implemented using digital circuits instead of analog components, enabling the PLL to function reliably at low power supply voltages (1.1V) without the design difficulties associated with analog circuits in advanced CMOS processes.
Solution Approach 2:
The patent changes the operating voltage parameter from traditional analog voltage levels to low voltage (1.1V) by transitioning to digital implementation. This parameter change enables the PLL to operate effectively in advanced CMOS processes where analog building blocks become difficult to design and power consumption increases.
2Reliability
If conventional analog building blocks are used in phase locked loops, then the PLL can be implemented traditionally, but power consumption increases at low power supply voltages
Solution Approach 1:
The patent replaces analog building blocks with digital building blocks, which consume less power at low voltage operations. The digital phase detector, counter, and logic circuits replace power-hungry analog operation amplifiers and current mirrors, reducing overall power consumption while maintaining PLL functionality at 1.1V power supply.
3Reliability
If analog PLL is implemented, then PLL functions can be performed, but large silicon area is required making it expensive in advanced CMOS processes
Solution Approach 1:
The patent substitutes digital circuits for analog circuits in the PLL implementation. Digital circuits generally occupy less silicon area compared to analog circuits requiring large operational amplifiers, current mirrors, and analog filter components. This substitution reduces the overall silicon area while maintaining PLL functionality.
4Speed
If digital circuits operate at higher speeds, then operating performance improves, but implementing analog PLL becomes more difficult in advanced processes
Solution Approach 1:
The patent replaces the analog implementation with a digital implementation that is better suited for high-speed operation in advanced CMOS processes. The digital phase detector, counter, and control logic can operate at higher speeds with better manufacturing yield compared to analog circuits in sub-micron processes.
Data Source
AI summary
A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.