Phase-to-Digital Converter Using Delay Lines for Low-Power ADPLL
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Solution Overview
Problem
Conventional analog phase-locked loops (PLLs) face challenges in design and implementation at low power supply voltages and in advanced CMOS processes, such as 65nm, due to inefficiencies in analog building blocks and increased silicon area costs, making it difficult to achieve stable frequency references for digital and analog applications.
Innovation Solution
An all-digital phase-locked loop (ADPLL) with a phase-to-digital converter (PDC) that converts analog phase information into a digital word, using tapped delay lines and looped feedback counters to measure phase differences, allowing for reduced power consumption and smaller silicon area, and supporting both fine and coarse phase conversions with high linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional analog building blocks are used in advanced CMOS processes at low power supply voltage, then the circuit can be implemented, but the operation becomes unreliable and design becomes difficult
Solution Approach 1:
The patent replaces conventional analog building blocks with digital building blocks in the PLL circuit. Specifically, analog components such as analog filters and voltage-controlled oscillators are substituted with digital equivalents including digital filters and digitally-controlled oscillators, enabling reliable operation at low power supply voltages (e.g., 1.1V) in advanced CMOS processes while simplifying the design process
Solution Approach 2:
The patent changes the operating parameters by transitioning from analog voltage-level operations to digital logic-level operations. This parameter change allows the circuit to function reliably at reduced supply voltages where analog circuits would fail, as digital circuits have inherent noise margins and threshold voltages that provide robust operation even at low voltage levels
2Reliability
If conventional analog PLL is implemented, then the filter function can be achieved, but the silicon area becomes large
Solution Approach 1:
The patent substitutes analog filter circuits with digital filter circuits in the PLL architecture. The digital filter processes phase error signals in the digital domain, eliminating the need for large-area analog components such as RC filters or switched-capacitor filters, thereby significantly reducing the overall silicon area while maintaining the necessary filtering functionality
Solution Approach 2:
The digital building blocks used in the patent can perform multiple functions. For example, the digital filter can simultaneously filter phase error signals and implement loop bandwidth control, while digitally-controlled oscillators can provide both frequency synthesis and phase adjustment capabilities, reducing the total component count and silicon area required
3Area of stationary object
If digital building blocks are used to implement PLL, then the silicon area is reduced, but the phase measurement precision must be maintained
Solution Approach 1:
The patent segments the phase measurement function into multiple digital components working together. The phase detector divides phase difference measurement into discrete digital pulses, the digital filter processes these pulses through multiple stages, and the digitally-controlled oscillator divides the measurement into frequency domains. This segmentation allows high-precision phase measurement to be achieved through digital signal processing rather than analog continuity, reducing silicon area while maintaining precision
Solution Approach 2:
The patent introduces digital intermediaries such as pulse generators, counters, and digital signal processors that mediate between the phase detector output and the final control signal. These digital intermediaries convert analog phase information into digital representations that can be processed with high precision using standard digital logic circuits, maintaining measurement accuracy while enabling area-efficient implementation
Data Source
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Figure 3A~3B
AI summary
A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.