Phase Discriminator Circuit for Noise-Isolated Clock Recovery

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Solution Overview

Problem

Existing clock and data recovery systems face issues with noise coupling and discontinuous phase adjustment, leading to increased bit error rates due to the direct connection of switch arrays to VCO control lines, which complicates achieving best sampling.

Innovation Solution

A phase discriminator with current mode logic XOR gates and offset current source circuits that adjust the amplitude of error and reference signals to control the phase of the clock signal, preventing noise coupling and enabling continuous phase adjustment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If switch arrays are directly connected to VCO control lines for phase adjustment, then phase adjustment function is achieved, but noise coupling into VCO increases causing clock phase jitter

Engineering Contradiction:
Improvephase adjustment capabilityVSAvoidclock phase stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces an intermediary mechanism by implementing phase adjustment through current source arrays that control the error signal amplitude in the phase discriminator, rather than directly connecting switch arrays to VCO control lines. This intermediary approach allows phase adjustment while isolating the VCO from noise coupling through the filter circuit, thus maintaining clock phase stability while preserving phase adjustment capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If discontinuous phase adjustment with switch arrays is used, then phase adjustment is simplified, but best sampling point cannot be accurately achieved increasing bit error rate

Engineering Contradiction:
Improvephase adjustment structureVSAvoidsampling point accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements dynamic phase adjustment by making the error signal amplitude controllable through current source arrays, allowing continuous or fine-grained adjustment of the phase discriminator's output. This dynamic control mechanism enables accurate positioning of the sampling point at the best instant by adjusting the error signal amplitude in response to phase differences, thereby achieving high sampling precision while maintaining reasonable device complexity.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If more switch arrays are used for higher phase adjustment precision, then sampling accuracy improves, but device complexity and resource occupation increase

Engineering Contradiction:
Improvephase adjustment precisionVSAvoidnumber of switch arrays
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the control parameter from direct voltage control of VCO to amplitude control of the error signal in the phase discriminator. By adjusting the error signal amplitude through current source arrays, the system achieves phase adjustment with fewer components. This parameter transformation allows high precision phase adjustment while reducing the number of switch arrays needed, as the adjustment is achieved through current modulation rather than multiple voltage control paths.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8624630B2Clock and data recovery system, phase adjusting method, and phasedetector
Publication Date: 2014.01.07 SANECHIPS TECH CO LTD
  • US8624630B2 patent drawing
  • US8624630B2 patent drawing
  • US8624630B2 patent drawing

AI summary

Disclosed is a phase discriminator, including: a first XOR gate connected to a trigger and a delay unit, a second XOR gate connected to the trigger and a latch, wherein the first XOR gate is a current mode logic XOR gate, the first XOR gate comprises a first offset current source circuit outputting a first adjustable offset circuit for controlling amplitude of the error signal output by the first XOR gate; and/or, the second XOR gate is a current mode logic XOR gate, the second XOR gate comprises a second offset current source circuit outputting a second adjustable offset circuit for controlling amplitude of reference signal output by the second XOR gate. Also disclosed are a clock and data recovery system and a phase adjustment method. The present invention can prevent introducing noise coupling to the voltage control oscillator (VCO) module.