Phase Doubler Driver Circuit Dynamic Current Balancing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase doubler circuits face challenges in maintaining current balance, especially during high-frequency transient events, leading to inefficiencies and potential damage due to uneven current distribution between phases.
Innovation Solution
A phase swapping scheme is implemented, where the PWM signal is dynamically routed to the phase with the lower current to maintain balance, using a current comparison circuit and a JK flip-flop to determine which phase to prioritize, thereby adjusting the PWM pulse distribution to balance currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional phase doubler circuits are used to generate multiple phases from a single PWM signal, then the phase count is increased, but current imbalance occurs between phases during transient events
Solution Approach 1:
The patent implements dynamic phase swapping by monitoring current levels in each phase and actively switching the PWM signal assignment between phases when imbalance is detected. This dynamic adjustment mechanism allows the system to adapt to transient conditions and maintain current balance, resolving the contradiction between increased phase count and current balance reliability
Solution Approach 2:
The system employs current sensing circuits that continuously monitor the current level in each phase and feed this information back to the control logic. This feedback mechanism enables the controller to detect current imbalance and trigger phase swapping operations, ensuring that the increased phase count does not compromise current distribution reliability
2Productivity
If PWM signals are distributed to multiple phases simultaneously, then phase count increases, but current imbalance and efficiency losses occur
Solution Approach 1:
The patent implements dynamic phase swapping by monitoring current levels in each phase and actively switching the PWM signal assignment between phases when imbalance is detected. This dynamic adjustment mechanism allows the system to adapt to transient conditions and maintain current balance, resolving the contradiction between increased phase count and current balance reliability
Solution Approach 2:
The system changes the operational parameters of the phase doubler by dynamically altering which phase receives the PWM signal based on real-time current measurements. This parameter change approach allows the system to optimize current distribution and minimize energy losses while maintaining the benefits of increased phase count
3Reliability
If phase swapping is implemented to balance currents, then current balance improves, but control complexity increases
Solution Approach 1:
The phase swapping mechanism operates autonomously based on simple current comparison logic. The control system automatically detects current imbalance and executes phase swapping without requiring complex external control, thereby improving current balance while minimizing the increase in control complexity
Data Source
AI summary
A phase doubler driver circuit includes first control logic generates a first output PWM drive signal and a second output PWM drive signal responsive to an input PWM drive signal. In a first mode of operation, alternating pulses of the input PWM drive are output as the first output PWM drive signal and the second PWM output drive signal respectively. In a second mode of operation, the input PWM drive signal is provided as the first output PWM drive signal when a second phase current associated with the second output PWM drive signal exceeds a first phase current associated with the first output PWM drive signal and the input PWM drive signal is provided as the second output PWM drive signal when the phase current associated with the first output PWM signal exceed the phase current associated with the second output PWM signal. Second control logic adds an offset to a falling edge of the first output PWM drive signal responsive to a difference between a first current associated with the first phase current and an average current and for adding the offset to a falling edge of the second output PWM signal responsive to a difference between a second current associated with the second phase current.