Multi-phase clock generator phase error correction loop
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Solution Overview
Problem
Existing multi-phase clock signal generation methods introduce errors and instability as the number of phases increases, particularly at high frequencies and low supply voltages, requiring complex and costly buffer designs to maintain correction range and accuracy.
Innovation Solution
A phase error correction loop that bypasses the buffer circuit, providing the phase error signal directly to a phase divider, allowing for constant loop gain across a wide range of frequencies and phases, enabling efficient correction of phase errors in a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-phase clock signal generation methods are used, then the system can generate multi-phase clock signals, but phase errors and instability increase as the number of phases increases
Solution Approach 1:
The patent extracts and removes the buffer circuit from the phase error correction loop, directly connecting the phase error correction circuit to the phase reference generator. This elimination of the buffer circuit reduces device complexity while maintaining phase error correction stability across multiple phases.
Solution Approach 2:
The patent implements a phase error correction loop that continuously monitors phase errors and feeds correction signals back to the phase reference generator. This feedback mechanism maintains reliability and stability of phase error correction even as the number of phases increases, without requiring complex buffer circuits.
2Measurement precision
If buffer circuits are used to maintain correction range and accuracy, then phase error correction accuracy is maintained, but device complexity and cost increase
Solution Approach 1:
The patent removes the buffer circuit from the signal path, directly connecting the phase error correction circuit output to the phase reference generator input. This extraction eliminates the source of complexity and cost while maintaining correction accuracy through direct signal transmission.
Solution Approach 2:
The phase reference generator serves as an intermediary that directly receives correction signals without requiring a buffer circuit. This intermediary approach maintains signal integrity and correction accuracy while avoiding the complexity of buffer designs.
3Speed
If the phase error correction loop includes a buffer circuit, then signal transmission is provided, but loop gain varies across different frequencies
Solution Approach 1:
By removing the buffer circuit from the loop, the patent eliminates the frequency-dependent gain variations that buffers introduce. The direct connection maintains constant loop gain across the wide frequency range from 400 KHz to 2.5 MHz, achieving both speed coverage and gain stability.
4Reliability
If complex buffer designs are used to maintain correction range, then correction accuracy is maintained, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the buffer circuit from the design, directly connecting the phase error correction circuit to the phase reference generator. This simplification reduces manufacturing cost by removing complex buffer designs while maintaining correction range and reliability through the direct connection path.
Data Source
AI summary
A multi-phase clock generator circuit includes a phase reference generator circuit configured to generate a phase reference signal in response to a phase selection signal and a peak ramp signal. A phase error correction circuit is configured to provide an error signal based on a synchronization clock signal and a multi-phase clock signal. The error signal is applied to the phase reference signal to correct for phase errors in the multi-phase clock signal. A comparator is configured to compare a ramp signal and the phase reference signal to produce the multi-phase clock signal.