Phase Error Determination Circuit for Integrated Circuits
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Solution Overview
Problem
Temperature and voltage variations in integrated circuits cause drift in clock signals, leading to timing offsets in data transmission, which can result in incorrect data values, and existing solutions like phase-locked loops and delay-locked loops require additional die area and power, and are slow to lock.
Innovation Solution
A circuit that corrects common phase errors by shifting phases of periodic signals used to sample input signals, utilizing a phase error determination circuit and periodic signal generators to apply a common phase shift to sampling clock signals, ensuring accurate data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-locked loops or delay-locked loops are used to reduce drift in transmitter clock signal, then timing offset is reduced, but die area increases and power consumption increases
Solution Approach 1:
The patent extracts the phase error determination function from complex PLL/DLL circuits and implements it using a simplified test signal-based measurement approach. By separating the phase measurement function from the clock generation function, the solution achieves timing correction without requiring large-area locked-loop circuits.
Solution Approach 2:
The patent uses test signals that copy the characteristics of actual data signals to measure phase error. By transmitting test signals through the same clock distribution network and measuring their phase relationship with receiver clock signals, the system determines phase error without needing complex correction circuits.
2Reliability
If phase-locked loops or delay-locked loops are used to reduce drift in transmitter clock signal, then timing offset is reduced, but power consumption increases
Solution Approach 1:
The patent extracts the phase error determination function from power-hungry PLL/DLL circuits and implements it using a simplified test signal-based measurement approach. By separating the phase measurement function from the clock generation function, the solution achieves timing correction without requiring high-power locked-loop circuits.
Solution Approach 2:
The patent uses simple test signals instead of complex locked-loop circuits to determine phase error. These test signals are transmitted temporarily to measure phase relationship and can be discarded after measurement, avoiding the continuous power consumption of PLL/DLL circuits.
3Reliability
If phase-locked loops or delay-locked loops are used to reduce drift in transmitter clock signal, then phase and frequency locking is achieved, but lock time increases after waking from low power state
Solution Approach 1:
The patent performs phase error measurement using test signals immediately after waking from low power state, before actual data transmission begins. This preliminary measurement allows the system to determine phase error quickly without waiting for PLL/DLL locking, enabling faster resumption of data transmission.
Solution Approach 2:
The patent skips the slow locking process of PLL/DLL circuits by using a faster test signal-based phase measurement method. The test signal approach rushes through the phase determination step that would otherwise require time-consuming locked-loop convergence.
Data Source
AI summary
An integrated circuit includes samplers, a phase error determination circuit, and periodic signal generators. The samplers generate respective sampled signals by sampling respective input signals in response to respective periodic signals. The input signals have a common phase error. The phase error determination circuit receives the sampled signals from the samplers. The phase error determination circuit generates a representation of the common phase error of the input signals in response to sampled signals received in a set-up mode in which the samplers sample respective input signals having a common bit pattern. The periodic signal generators generate the periodic signals differing in phase from one another by defined phase differences in the set-up mode and subject the periodic signals to a common phase shift in a normal mode in response to the representation of the common phase error. The common phase shift matches the common phase error of the input signals.