Phase Frequency Detector Dead Zone Elimination
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Solution Overview
Problem
Conventional phase frequency detectors in digital PLL systems suffer from the 'dead zone' phenomenon and limited counting resolution due to delay in the reset path, which prevents detection of phase errors smaller than a clock signal.
Innovation Solution
A phase frequency detector design incorporating a phase error detector, a phase error judgment unit, and a reset unit that outputs synchronized reset signals to reset both units, utilizing D-type flip-flops and NOR gates to ensure proper propagation delays and enhance counting resolution, even for phase errors less than one clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional PFD with AND gate reset path is used, then the circuit structure is simple, but the counting resolution is limited and dead zone phenomenon occurs
Solution Approach 1:
The patent divides the reset function into two separate reset paths: one reset path for the phase error detector and another reset path for the phase error judgment unit. This segmentation allows independent control of reset timing for each unit, eliminating the dead zone phenomenon and improving counting resolution without requiring a completely complex new architecture
Solution Approach 2:
The patent introduces a phase error judgment unit that performs preliminary judgment on phase error before the main phase error detector processes it. This preliminary action allows the system to prepare reset signals in advance based on phase error conditions, ensuring accurate counting even for small phase errors less than one clock cycle
2Measurement precision
If the reset path delay is reduced, then the counting resolution improves, but the circuit complexity increases
Solution Approach 1:
By segmenting the reset function into two independent reset paths with separate control logic, the patent eliminates the need for complex delay compensation circuits. Each reset path can be optimized independently, reducing overall reset path delay while maintaining manageable circuit complexity
Solution Approach 2:
The phase error judgment unit acts as an intermediary that generates appropriate reset control signals based on phase error conditions. This intermediary structure simplifies the reset path timing control compared to direct complex delay compensation, improving phase error detection accuracy while keeping the circuit structure relatively simple
Data Source
AI summary
A phase frequency detector includes a phase error detector outputting a phase error signal according to a first input signal and a second input signal; a phase error judgment unit outputting a phase error judgment signal according to the first input signal and the second input signal; and a reset unit outputting a first reset signal to reset the phase error detector, and outputting a second reset signal to reset the phase error judgment unit, according to the phase error judgment signal.