Phase-Frequency Detector Circuit for Faster PLL Frequency Lock
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Solution Overview
Problem
Existing phase and frequency detectors in phase locked loops (PLLs) face challenges in efficiently generating an output signal proportional to the frequency difference between two input signals, particularly in multi-core processor applications where fine frequency increments are needed, but existing mechanisms are power-intensive and limited in frequency change rate.
Innovation Solution
A phase and frequency detector circuit that includes edge-detector latches and output latches, generating signals indicative of phase and frequency differences, allowing for proportional frequency output, which can be used in loop filters to stabilize and quickly acquire frequency locks in PLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing phase and frequency detectors are used in PLLs, then frequency difference detection is achieved, but the output signal is not proportional to frequency difference and frequency acquisition is slow
Solution Approach 1:
The detector is divided into separate edge detector latches and output latches that independently process phase and frequency information. The edge detector latches generate phase difference signals while the output latches generate frequency-proportional signals, allowing simultaneous extraction of both phase and frequency error information without interference.
Solution Approach 2:
The patent transitions from traditional single-dimension phase detection to multi-dimensional detection by generating both phase difference signals and frequency-proportional signals from the same input signals. This dimensional expansion allows the system to simultaneously measure both phase and frequency differences, enabling faster frequency acquisition while maintaining measurement precision.
2Measurement precision
If fine frequency increments are implemented in multi-core processors, then frequency control precision is improved, but power consumption increases and frequency change rate is limited
Solution Approach 1:
The detector circuit automatically generates frequency-proportional output signals that directly indicate the magnitude and direction of frequency differences. This self-service capability eliminates the need for complex external frequency measurement and control circuits, reducing overall system power consumption while maintaining fine frequency control precision through the proportional output signals.
3Productivity
If proportional frequency output is generated, then frequency acquisition speed is improved, but circuit complexity increases
Solution Approach 1:
The patent merges phase detection and frequency detection functions into a single integrated detector circuit. The edge detector latches and output latches work together to simultaneously generate both phase difference and frequency-proportional signals from the same input clock signals, achieving fast frequency acquisition without requiring separate detection circuits.
Solution Approach 2:
The detector circuit performs multiple functions: it detects phase differences, detects frequency differences, and generates frequency-proportional output signals all within the same circuit structure. This multi-functionality reduces the need for additional dedicated circuits, thereby limiting the increase in overall system complexity while achieving improved frequency acquisition speed.
Data Source
AI summary
Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals.