Phase Interleaving Control for Multi-Channel Regulator Systems
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Solution Overview
Problem
Multi-channel regulator systems face limitations due to fixed master/slave configurations and inability to dynamically adjust the number of channels or enable/disable channels on the fly, leading to inflexibility and increased power ripples in input voltage.
Innovation Solution
A phase interleaving control method where each PWM IC determines its operation mode based on detected external clocks, allowing for dynamic rearrangement of master/slave configurations and enabling/disabling channels, using phase delays and internal clocks to maintain synchronization and interleaving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If decoupling capacitor Cde is increased to decrease ripples in input voltage Vin, then voltage ripple is reduced, but circuit size and costs increase and transient response degrades
Solution Approach 1:
The patent implements dynamic channel configuration where PWM ICs can transition between master and slave modes based on real-time detection of external clocks. This dynamic reconfiguration allows the system to adapt the number of active channels according to load requirements, reducing the need for oversized decoupling capacitors while maintaining voltage ripple performance.
Solution Approach 2:
The system changes operational parameters by allowing PWM ICs to switch between different operational states (master/slave modes) based on detected clock signals. This parameter change enables flexible adjustment of system behavior without requiring fixed hardware configurations or large decoupling capacitors.
2Reliability
If fixed master/slave configuration is used for phase interleaving, then clock synchronization is achieved, but system flexibility and adaptability are reduced
Solution Approach 1:
Each PWM IC dynamically determines its operational mode by detecting the presence or absence of external clocks from previous channels. This dynamic detection and mode switching capability allows the system to automatically adapt to different channel configurations while maintaining proper phase interleaving and clock synchronization.
Solution Approach 2:
PWM ICs autonomously determine their own operational mode (master or slave) by detecting external clock signals. This self-service mechanism eliminates the need for fixed external configuration and allows each IC to automatically adapt to system requirements, enhancing flexibility while maintaining synchronization.
3Reliability
If master channel must always remain enabled to provide synchronous clocks, then clock distribution is maintained, but power consumption increases and channel configurability is limited
Solution Approach 1:
The system dynamically redistributes clock generation responsibilities among PWM ICs based on their operational state. When a PWM IC transitions to master mode, it assumes clock generation duties, allowing previously active slave channels to be disabled without losing clock distribution capability. This dynamic role assignment reduces power consumption while maintaining reliable clock distribution.
4Device complexity
If fixed number of channels is configured, then system design is simplified, but ability to expand or reduce channels on the fly is lost
Solution Approach 1:
The patent implements dynamic channel configuration where the number of active channels can be adjusted in real-time based on load requirements. PWM ICs detect external clock signals to determine their operational mode, enabling seamless addition or removal of channels without requiring system redesign or fixed configuration.
Solution Approach 2:
Each PWM IC is designed to perform multiple functions - it can operate as either a master channel generating clocks or as a slave channel receiving clocks. This multi-functionality allows any PWM IC to adapt to different system configurations, enabling flexible channel expansion or reduction without increasing overall system complexity.
Data Source
AI summary
A multi-channel regulator system includes serially connected PWM integrated circuits, each of which determines a PWM signal for a respective channel to operate therewith, and individually controls its operation mode according to whether or not an external clock is detected. Therefore, each channel will not be limited to operate under a constant mode and could become a master channel or a slave channel. Additionally, each of the PWM integrated circuits generates a phase shifted synchronous clock for its next channel during it is enabled, and thus all the channels operate in a synchronous but phase interleaving manner.