Phase-Interpolated Clock Circuit for Fast Duty Cycle Correction
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Solution Overview
Problem
Existing methods for correcting duty cycle errors in clock signals are inefficient, requiring numerous iterative adjustments and taking hundreds of clock cycles, which can delay the operation of digital circuits and be undesirable in many applications.
Innovation Solution
A duty cycle corrected clock signal generator circuit that includes a clock generator, duty phase interpolator, and duty cycle adjuster, which uses phase interpolation and adjustable inverter drivers to quickly correct duty cycle errors, providing a duty cycle corrected clock signal with a 50% duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If adjustable delay circuits are used to correct duty cycle errors through iterative adjustment, then duty cycle accuracy is improved, but correction time increases significantly
Solution Approach 1:
The patent pre-calculates and stores optimal delay values in a lookup table before operation. When duty cycle correction is needed, the system simply retrieves the pre-computed value instead of performing iterative adjustments, thus achieving accurate correction without the time penalty of repeated iterations.
Solution Approach 2:
The patent replaces the mechanical iterative adjustment process with a computational approach using a lookup table. Instead of physically adjusting delay circuits through multiple iterations, the system uses pre-computed data and memory retrieval, substituting a fast electronic lookup operation for a slow mechanical adjustment process.
2Reliability
If iterative duty cycle correction is performed, then signal reliability is improved, but circuit operation is delayed
Solution Approach 1:
The optimal correction parameters are calculated and stored in advance in a lookup table. When the circuit needs to operate, it immediately retrieves the pre-computed correction value without waiting for iterative adjustments, thus maintaining signal reliability while eliminating the delay that would otherwise prevent circuit operation.
Solution Approach 2:
The system uses the input clock signal itself to generate the phase-interpolated clock signals through the lookup table mechanism. The correction process is self-contained and does not require external iterative adjustment, allowing the circuit to autonomously achieve reliable operation without delaying productivity.
3Speed
If phase interpolation with lookup table is used, then correction speed is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex real-time iterative adjustment circuitry with a simpler lookup table and phase interpolation logic. The computational complexity is shifted from runtime circuit operations to pre-computation and storage, resulting in faster correction speed with acceptable increase in memory requirements but reduced operational complexity.
Data Source
AI summary
Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input dock signal. A duty phase interpolator circuit may be coupled to the dock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected dock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error.