Phase-Interpolated Clock Generation Across Wide Frequency Ranges
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Solution Overview
Problem
Designing clock generators with a wide tunable frequency range is challenging due to issues such as poor jitter performance at low input biases and difficulty in controlling the clock phase, especially when providing a tunable frequency range by mapping to a range in the period between edges, which can result in unacceptable integrated non-linearity for the phase interpolator.
Innovation Solution
A circuit and method that scale a phase control value from an external phase control resolution to an internal phase control resolution, determine a phase step value based on the difference between current and target phase control values, and generate a phase controlled clock signal at both internal and external frequencies using a digital-to-phase converter and frequency divider, allowing for phase interpolation and stable frequency division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a wide tunable frequency range is provided by mapping to a range in the period between edges, then the frequency range is expanded, but the integrated non-linearity for the phase interpolator becomes unacceptable
Solution Approach 1:
The phase control range is segmented into multiple sub-ranges, each handled by a dedicated phase interpolator optimized for its specific range. This allows each interpolator to maintain linearity within its segment while collectively covering a wide frequency range, resolving the contradiction between wide tuning range and low non-linearity.
Solution Approach 2:
Different phase interpolators are designed with different characteristics optimized for specific frequency ranges. Each interpolator has locally optimized parameters to minimize non-linearity in its designated range, rather than using a single interpolator for the entire wide range, thus maintaining precision while achieving versatility.
2Adaptability or versatility
If the clock frequency is tuned over a wide range, then the frequency adaptability is improved, but the jitter performance deteriorates at low input biases
Solution Approach 1:
The system dynamically switches between different phase interpolators based on the current frequency range and input bias conditions. This dynamic adaptation allows the system to maintain optimal jitter performance across the entire frequency range by selecting the appropriate interpolator for current operating conditions, rather than using a fixed design that compromises performance.
Solution Approach 2:
The system changes parameters such as the number of interpolation taps and tap spacing based on the operating frequency range and input bias. By adapting these parameters dynamically, the system maintains low jitter performance across wide frequency ranges, resolving the contradiction between frequency adaptability and jitter performance.
3Measurement precision
If the phase control resolution is increased to improve phase control precision, then the phase control accuracy is improved, but the device complexity increases
Solution Approach 1:
Instead of increasing the resolution of a single phase interpolator (one-dimensional approach), the system uses multiple interpolators with coarser resolution that work together (multi-dimensional approach). This parallel structure achieves equivalent or better effective resolution while keeping each individual interpolator simple, thus improving phase control precision without proportionally increasing device complexity.
Data Source
AI summary
In certain embodiments, an apparatus may comprise a circuit configured to scale a phase control value from an external phase control resolution of an external clock frequency to an internal phase control resolution of an internal clock frequency to generate a target phase control value. The circuit may also determine a difference between a current phase control value and the target phase control value and determine a phase step value based on the difference. Further, the circuit may modify a current phase control value based on the phase step value and generate a phase controlled clock signal at the internal clock frequency using the modified phase control value. Additionally, the circuit may divide the phase controlled clock signal at the internal clock frequency to generate a phase controlled clock signal at the external clock frequency.