Phase-Interpolated Fractional Frequency Divider Circuit
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Solution Overview
Problem
Standard frequency dividers produce output frequencies that are integer multiples of the reference clock frequency, limiting applications that require fractional frequency multiples for wireless and clock generation units.
Innovation Solution
A phase interpolator generates an adjustable output clock signal with a phase offset, which is then divided by an integer factor using an integer-N divider, allowing for fractional frequency division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a standard integer-N divider is used, then the circuit structure is simple, but the output frequency can only be an integer multiple of the reference clock frequency
Solution Approach 1:
The frequency division function is segmented into two parts: an integer-N divider for the basic division and a phase interpolator for the fractional adjustment. This allows the system to achieve fractional frequency division by combining a simple integer divider with a phase interpolation mechanism, resolving the contradiction between simplicity and adaptability.
Solution Approach 2:
A phase interpolator is introduced as an intermediary component between the reference clock and the integer-N divider. The phase interpolator generates a clock signal with a phase offset that enables fractional frequency division when divided by the integer-N divider, thus achieving frequency adaptability without fundamentally changing the divider structure.
2Adaptability or versatility
If a phase interpolator is added to enable fractional frequency division, then the frequency adaptability is improved, but the device complexity increases
Solution Approach 1:
The system is segmented into a phase interpolator module and an integer-N divider module. The phase interpolator handles only the fractional phase adjustment function, while the integer-N divider handles the main frequency division, allowing each component to remain relatively simple while achieving complex fractional division capability overall.
Data Source
AI summary
An oscillator may output phased signals to a phase interpolator which is to generate an adjustable output clock signal having a phase offset relative to at least one of the phased signals received from the oscillator. A divider may then divide the frequency of the output signal generated by the phase interpolator by an integer factor.