Phase-Interpolated Time-to-Digital Converter for Lower Delay Count
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Solution Overview
Problem
Existing time-to-digital converters require a large number of delay units to ensure time accuracy, leading to increased circuit scale and power consumption when measuring significant phase differences between clock signals.
Innovation Solution
A time-to-digital converter that performs phase interpolation on reference clock signals to generate a third reference clock signal with a reduced phase difference, allowing for fewer delay units and a simpler circuit design, while maintaining time accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If more delay units are used to ensure time accuracy when measuring large phase differences, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the measurement process into two independent stages: first, the phase interpolation circuit segments the large phase difference into a smaller phase difference; second, the time-to-digital conversion circuit measures this reduced phase difference. This segmentation allows the use of fewer delay units in the second stage while maintaining measurement precision.
Solution Approach 2:
The phase interpolation circuit acts as an intermediary between the input clock signals and the time-to-digital conversion circuit. It processes the large phase difference first and outputs a third clock signal with a reduced phase difference, which is then easier to measure with fewer delay units.
2Measurement precision
If more delay units are used to ensure time accuracy when measuring large phase differences, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The measurement function is segmented into two circuits with different power consumption characteristics. The phase interpolation circuit handles the power-intensive phase adjustment, while the time-to-digital conversion circuit uses fewer delay units and consumes less power for the actual measurement of the reduced phase difference.
Solution Approach 2:
The phase interpolation circuit serves as a power-reducing intermediary by performing the energy-intensive phase adjustment before the measurement stage, thereby reducing the power consumption of the subsequent time-to-digital conversion circuit.
3Measurement precision
If more delay units are used to ensure time accuracy when measuring large phase differences, then measurement precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the measurement system into two functional blocks, allowing optimization of each for manufacturing. The phase interpolation circuit uses standard components for phase adjustment, while the time-to-digital conversion circuit requires fewer delay units, reducing overall component count and manufacturing cost.
Data Source
AI summary
The present invention discloses a time-to-digital converter. The time-to-digital converter includes: a phase interpolation circuit and a time-to-digital conversion circuit. The phase interpolation circuit is configured to receive a first reference clock signal and a second reference clock signal; perform phase interpolation on the first reference clock signal and the second reference clock signal to generate a third reference clock signal; and output the third reference clock signal to the time-to-digital conversion circuit. The time-to-digital conversion circuit is configured to receive the third reference clock signal and a fourth clock signal, where a phase difference between the third reference clock signal and the fourth clock signal is less than a phase difference between the first reference clock signal and the fourth clock signal; measure the phase difference between the third reference clock signal and the fourth clock signal; and convert the measured phase difference into a digital signal for outputting.