Low-Voltage Phase Interpolation Circuit With Dithering Suppression

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Solution Overview

Problem

Conventional phase interpolation circuits face limitations in operating at low voltages and suffer from phase shift errors and 3-code dithering issues, which affect synchronization between microprocessors and peripheral devices in digital technologies.

Innovation Solution

A phase interpolation circuit that precharges an output node to a power supply voltage, discharges it using inverse proportionality-controlled current sources, and includes a comparison unit and short pulse generation to minimize phase shift and detect/deter 3-code dithering, utilizing a D/A converter and current mirror circuits to manage current flow effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If conventional phase interpolation circuits are used, then phase interpolation can be achieved, but the circuit cannot operate at low voltages and suffers from phase shift errors

Engineering Contradiction:
Improvevoltage levelVSAvoidphase shift error
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent applies preliminary action by precharging the output node to a power supply voltage level before the actual phase interpolation operation. This precharging step ensures that the output node is in a known state and ready for the subsequent discharge phase, which enables the circuit to operate reliably at low voltages by establishing proper initial conditions that prevent phase shift errors during the interpolation process

Inventive Principle:
Principle #10Preliminary action

2Speed

If conventional phase interpolation circuits are used, then clock signal generation is achieved, but 3-code dithering occurs affecting synchronization

Engineering Contradiction:
Improvesynchronization accuracyVSAvoiddithering stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements feedback by continuously monitoring the output signal and adjusting the interpolation control signal based on the detected phase difference. This feedback mechanism detects and corrects dithering conditions in real-time, preventing 3-code dithering from occurring and ensuring stable synchronization between clock signals while maintaining high speed operation

Inventive Principle:
Principle #23Feedback

3Measurement precision

If conventional phase interpolation circuits are used, then phase control is achieved, but the circuit complexity increases with additional components

Engineering Contradiction:
Improvephase accuracyVSAvoidcircuit component count
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a phase interpolation circuit where the same core components perform multiple functions. The output node serves both as the interpolation output and the comparison input, the current source unit handles both charging and discharge operations, and the comparison unit integrates both phase detection and dithering detection functions. This multi-functionality reduces the overall component count while maintaining high phase accuracy

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7551013B2Phase interpolation circuit and method of generating phase interpolation signal
Publication Date: 2009.06.23 SAMSUNG ELECTRONICS CO LTD
  • US7551013B2 patent drawing
  • US7551013B2 patent drawing
  • US7551013B2 patent drawing

AI summary

A phase interpolation circuit and method are provided that are capable of operating in a low voltage and capable of generating a substantially exact phase-interpolation signal, where the phase interpolation circuit is configured to output a phase interpolation signal having a phase between phases of at least two input signals and comprises an interpolation unit configured to discharge an output node by a first interpolation control signal in case a first input signal of two input signals having different phases is inputted to the interpolation unit when the output node has been precharged to a power supply voltage level, the interpolation unit additionally discharging the output node by a second interpolation control signal in case of input of a second input signal of the two input signals; a comparison unit for comparing a reference voltage level and a voltage level of the output node of the interpolation unit to output a signal corresponding to the comparison; and a short pulse generation unit for generating a short pulse in response to an output signal of the comparison unit.