Phase Interpolation Circuit with Standby Voltage Control for Linearity
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Solution Overview
Problem
The scalable INV-type phase interpolation circuit has limitations in linearity of phase interpolation, particularly at high signal speeds, which affects the accuracy of phase interpolation.
Innovation Solution
The phase interpolation circuit includes a current control unit with slice circuits that utilize PMOS and NMOS transistors, current sources, and standby voltage set circuits to improve linearity by managing parasitic capacitance and stabilizing output currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a scalable INV-type phase interpolation circuit is used, then power consumption is reduced and size is minimized, but linearity of phase interpolation deteriorates
Solution Approach 1:
The phase interpolation circuit is divided into multiple slice circuits (first slice circuit, second slice circuit, etc.), each handling a portion of the phase interpolation task. This segmentation allows the INV-type circuit to achieve better linearity by distributing the interpolation function across multiple stages while maintaining low power consumption and compact size characteristics of the original circuit architecture.
2Productivity
If signal speed increases, then productivity is improved, but linearity of phase interpolation deteriorates
Solution Approach 1:
Standby voltage set circuits are introduced to pre-charge or pre-discharge parasitic capacitances in each slice circuit before the actual phase interpolation operation. This preliminary action prepares the circuit nodes in advance, reducing the impact of parasitic effects during high-speed operation and maintaining linearity even at increased signal speeds.
3Use of energy by moving object
If manufacturing process node is reduced for low voltage operation, then power consumption is reduced, but voltage headroom becomes insufficient causing phase accuracy deterioration
Solution Approach 1:
The circuit employs dynamic voltage control through standby voltage set circuits that adjust the voltage levels at critical nodes during operation. This dynamic approach compensates for the reduced voltage headroom available in fine process nodes, maintaining sufficient signal swing and phase accuracy while operating at low supply voltages required for power-efficient operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the linearity of phase interpolation, reducing phase errors and improving the accuracy of phase interpolation, especially at high signal speeds.
Implementation Method 1
a first standby voltage set circuit configured to set a first node between the drain of the PMOS transistor and the first current source to a standby voltage by charging and discharging a parasitic capacitance at the first node
Data Source
AI summary
A current control unit 10 of a phase interpolation circuit 1 includes M slice circuits 60B0 to 60BM-1 having a common configuration. Each slice circuit 60Bm includes a selector 61, a PMOS transistor 62, an NMOS transistor 63, a PMOS transistor 64, an NMOS transistor 65, a first standby voltage set circuit 70, and a second standby voltage set circuit 80. The first standby voltage set circuit 70 has a configuration connecting the first node N1 and the voltage source via a switch the on/off of which is set according to the output signal from the selector 61, and sets the first node N1 to a standby voltage by supplementarily charging and discharging the parasitic capacitance of the first node N1 when the switch is in the on state.