Phase Interpolator DAC Using 2D Thermometer Codes for Glitch-Free Clocks
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in synchronizing the operating speed of peripheral devices with processors, leading to inefficiencies in data transmission due to disparities in clock signal synchronization, particularly in communication devices where phase interpolators fail to maintain monotonic and glitch-free characteristics with limited control signals.
Innovation Solution
A phase interpolator is designed with a digital-to-analog converter controlled by two-dimensional thermometer codes, comprising a decoder, digital-to-analog converter, and phase mixer, which generates a phase interpolation clock signal by adjusting unit cells to achieve improved differential non-linearity, glitch-free, and monotonic performance even with a small number of control bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a phase interpolator uses a conventional digital-to-analog converter with limited control bits, then the device complexity is reduced, but the differential non-linearity performance deteriorates and glitch-free characteristics cannot be maintained
Solution Approach 1:
The patent applies two-dimensional thermometer codes instead of conventional one-dimensional codes to control the DAC. This dimensional transformation allows the system to achieve finer phase resolution and maintain monotonicity with fewer control bits, effectively resolving the contradiction between device complexity and manufacturing precision
Solution Approach 2:
The phase interpolation range is divided into multiple segments, each controlled by a specific unit cell in the DAC. By segmenting the control function across multiple unit cells and using two-dimensional coding, the system achieves high precision differential non-linearity control without increasing overall device complexity
2Productivity
If the phase interpolator operates at higher speeds to match processor speeds, then the productivity is improved, but glitches and non-monotonic behavior occur due to synchronization issues with peripheral devices
Solution Approach 1:
The patent implements a feedback mechanism where the phase interpolator continuously monitors and adjusts its output based on the actual phase difference between clock signals. This feedback control ensures monotonic operation and eliminates glitches even at high operating speeds, maintaining reliability while improving productivity
Solution Approach 2:
The phase interpolator uses dynamic control signals that continuously adapt to changing phase conditions. By making the control signals dynamic rather than static, the system can operate at higher speeds while maintaining monotonic characteristics and avoiding glitches
3Manufacturing precision
If the phase interpolator uses more control bits to improve precision, then the manufacturing precision is improved, but the device complexity increases
Solution Approach 1:
The patent transforms the control structure from one-dimensional to two-dimensional thermometer codes. This dimensional change enables the system to achieve higher phase resolution (better manufacturing precision) without proportionally increasing the number of control bits or device complexity, as the two-dimensional structure encodes more information more efficiently
Data Source
AI summary
A phase interpolator includes a decoder, a digital-to-analog converter (DAC), and a phase mixer. The decoder generates first and second thermometer codes and a selection signal based on a code. The DAC includes unit cells, determines two of weight signals as first and second target weight signals based on the selection signal, and adjusts a current of the first and second target weight signals by controlling the unit cells based on the first and second thermometer codes and the selection signal. The phase mixer determines two of input clock signals as first and second target clock signals and generates an output clock signal based on the first and second target weight signals and the first and second target clock signals. A phase of the output clock signal is between phases of the first and second target clock signals. The unit cells include different first and second unit cells.