Quadrant-Switching Phase Interpolator With Bit-Shift Phase Control
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Solution Overview
Problem
Conventional phase interpolators have high hardware complexity, leading to large parasitic capacitance and limited phase update rates, causing jitter and potential clock signal loss during quadrant switching in high-speed applications.
Innovation Solution
A quadrant alternate switching phase interpolator using two multiplexer circuits and a controller circuit to generate an output clock signal by performing bit-shift operations on phase control bits, reducing hardware complexity and jitter by alternately switching only one output of the multiplexers during phase adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple four-to-one multiplexers and multiple phase buffers are used to switch quadrants, then quadrant switching capability is achieved, but hardware complexity increases and parasitic capacitance increases
Solution Approach 1:
The phase interpolator is divided into four separate phase interpolation circuits, each handling a specific quadrant. Each circuit uses a two-to-one multiplexer and processes only the phase signals within its assigned quadrant range, reducing the complexity of each individual circuit while maintaining overall quadrant switching capability.
Solution Approach 2:
The patent implements dynamic quadrant switching by selectively enabling or disabling specific phase interpolation circuits based on the desired output phase quadrant. The system dynamically activates only the necessary circuit(s) for the current quadrant, reducing parasitic capacitance and improving phase update rate compared to having all circuits continuously active.
2Adaptability or versatility
If all multiplexer outputs are switched during quadrant transition, then quadrant switching is achieved, but jitter increases and clock signal may disappear
Solution Approach 1:
The patent pre-calculates and prepares the phase signals for the target quadrant before switching occurs. The phase interpolation circuits continuously generate phase signals for all quadrants, but only the signals for the current quadrant are actively connected to the output. This preliminary preparation ensures smooth transitions without jitter or signal loss.
Solution Approach 2:
The patent introduces phase buffer circuits as intermediaries between the phase interpolation circuits and the output. These buffers act as isolation elements that allow seamless switching between quadrants by maintaining signal integrity during transitions, preventing jitter and ensuring continuous clock signal output.
3Ease of operation
If conventional phase interpolator structure is used, then phase interpolation function is provided, but phase update rate is limited due to large parasitic capacitance
Solution Approach 1:
By segmenting the phase interpolator into four independent phase interpolation circuits, each handling a specific quadrant, the parasitic capacitance of each circuit is significantly reduced. This segmentation allows for faster phase updates within each quadrant while maintaining the overall phase interpolation function across the full 360-degree range.
Solution Approach 2:
The patent changes the operational parameters by using two-to-one multiplexers instead of four-to-one multiplexers in each circuit segment. This parameter change reduces the switching capacitance and improves the phase update rate, enabling high-speed phase interpolation while maintaining the required interpolation accuracy.
Data Source
AI summary
A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.