Fixed-Frequency Phase Interpolator for Multi-Standard CDR Linearity
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits face challenges in achieving high-linearity phase interpolation across multiple standards while maintaining noise immunity, often requiring trade-offs between linearity and noise sensitivity due to limitations in frequency range and edge-rate adjustments.
Innovation Solution
A high-linearity Phase Interpolator-based CDR circuit that operates at a fixed high frequency, divides the output clock to match each standard, and uses a finite state machine to adjust the clock pair's phase and frequency, ensuring maximum phase linearity and reduced noise sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CDR circuit operates at variable frequencies to match different data rate standards, then adaptability to multiple standards is improved, but phase linearity deteriorates due to frequency-dependent edge-rate variations
Solution Approach 1:
The patent applies parameter changes by operating the phase interpolator at a fixed high frequency rather than varying it with data rate. The frequency adaptation is achieved through a divider that divides the fixed high-frequency clock by different factors (N=1, 2, or 4) to produce the appropriate frequency for each data rate standard. This maintains optimal edge-rates and phase linearity in the interpolator while still supporting multiple standards through the frequency division mechanism.
2Adaptability or versatility
If the CDR circuit adjusts edge-rates for different data rates, then adaptability to multiple standards is improved, but noise sensitivity increases due to reduced phase linearity
Solution Approach 1:
The patent maintains the phase interpolator operating at a fixed high frequency with optimized edge-rates, preventing noise sensitivity increases. The adaptability to different data rates is achieved not by changing the interpolator frequency or edge-rates, but by using a programmable divider that divides the stable high-frequency clock by different factors. This decoupling of frequency adaptation from edge-rate adjustment preserves phase linearity and noise immunity across all standards.
3Use of energy by moving object
If the CDR circuit operates at lower frequencies for lower data rates, then power consumption is reduced, but phase linearity deteriorates due to suboptimal edge-rates
Solution Approach 1:
The patent segments the frequency adaptation function from the phase interpolation function. The phase interpolator operates continuously at a fixed high frequency with optimal edge-rates, while a separate divider circuit handles the frequency scaling for different data rates. This segmentation allows the interpolator to maintain optimal performance characteristics regardless of the output data rate, eliminating the trade-off between power consumption and phase linearity.
Solution Approach 2:
The patent changes the approach to frequency adaptation by using a divider rather than directly scaling the interpolator frequency. The interpolator frequency remains constant at an optimized value, and the output frequency is adjusted by changing the division factor N. This parameter change in the operating frequency of the interpolator maintains optimal edge-rates and phase linearity while still supporting multiple data rate standards through the divided output clock.
Data Source
AI summary
A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.