Phase Interpolator Channel Switching for Wideband High-Speed CDR
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Solution Overview
Problem
Conventional phase interpolators face a trade-off between operation frequency range and maximum operation speed due to parasitic capacitive effects, making it difficult to ensure both performance metrics simultaneously.
Innovation Solution
A phase interpolator design incorporating a phase interpolation circuit, low pass filtering channels with switches and capacitors, and a multiplexing circuit that selectively uses channels with different capacitances to minimize parasitic capacitive effects, allowing for a wide operation frequency range without reducing maximum speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a switch capacitor array is added at the output terminal to increase operation frequency range, then the operation frequency range is improved, but the maximum operation speed is reduced due to increased parasitic capacitance
Solution Approach 1:
The patent divides the single output terminal into multiple output terminals (first output terminal and second output terminal), each with its own switch capacitor array. This segmentation allows different capacitance values to be selectively applied at different frequency ranges, resolving the contradiction between wide frequency range and high maximum speed by preventing parasitic capacitance accumulation at any single terminal.
Solution Approach 2:
The patent dynamically switches between different output terminals based on the operating frequency range. A selection circuit chooses which output terminal to use depending on the desired frequency range, enabling the system to optimize for either wide frequency coverage or maximum speed at any given moment, thus resolving the static trade-off between these two parameters.
2Adaptability or versatility
If the effective capacitance at the output terminal is increased to extend frequency range, then the operation frequency range is improved, but the maximum operation speed is reduced
Solution Approach 1:
The patent applies different capacitance characteristics to different output terminals. Each output terminal has a switch capacitor array with specific capacitance values optimized for particular frequency ranges. This local quality differentiation allows the system to have high capacitance (for frequency range) where needed and low capacitance (for speed) where needed, resolving the contradiction between frequency range extension and speed maintenance.
Data Source
AI summary
A phase interpolator including a phase interpolation circuit, a plurality of low pass filtering channels, and a multiplexing circuit is provided. The phase interpolation circuit receives a first clock signal and a second clock signal and accordingly performs an interpolation operation to generate an output clock signal. The low pass filtering channels respectively have an output terminal and an input terminal that is coupled to the phase interpolation circuit to receive the output clock signal. Each of the low pass filtering channels includes a switch and a capacitor which are coupled to a common node as the output terminal. The multiplexing circuit has a plurality of input terminals respectively coupled to the output terminals of the low pass filtering channels. The multiplexing circuit selects an input signal received from one of the low pass filtering channels as a phase interpolation signal according to a selecting signal.