Phase Interpolator Delay Lines for Large Clock Phase Gaps
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Solution Overview
Problem
Conventional phase interpolators are unable to synthesize clocks with large phase differences, particularly when the clocks are low-frequency, as their transition periods do not overlap, making it impossible to generate a middle phase clock.
Innovation Solution
A phase interpolator design that includes a first delay line with an adjustable delay value based on a delay control code, a delay control circuit for phase comparison, and a second delay line with a delay value corresponding to half of the first delay line's value, allowing for the generation of a middle phase clock between clocks with significant phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional phase interpolator is used to synthesize clocks, then phase interpolation works for small phase differences, but it fails when the phase difference is large (transition periods do not overlap)
Solution Approach 1:
The phase interpolation process is segmented into multiple stages: first aligning clocks using a first delay line, then performing interpolation using a second delay line with half the delay value. This segmentation allows the system to handle large phase differences by breaking them into manageable steps, ensuring transition periods overlap at each stage.
Solution Approach 2:
Before performing phase interpolation, the system performs preliminary phase alignment by adjusting the first delay line to make transition periods of input clocks overlap. This preliminary action creates the necessary condition for successful interpolation by ensuring that clocks are synchronized to a degree where their transition periods coincide.
2Adaptability or versatility
If delay values are adjusted to align phases, then phase interpolation becomes possible, but additional delay control mechanisms are required
Solution Approach 1:
The system employs dynamic delay adjustment where the first delay line's delay value is continuously adjusted based on phase comparison results until transition periods overlap. This dynamic control enables adaptive phase alignment for various input conditions while maintaining a relatively simple overall structure through feedback-based adjustment.
Solution Approach 2:
A delay control circuit acts as an intermediary that compares phases of input clocks and generates appropriate delay control codes. This intermediary component simplifies the control mechanism by centralizing the phase comparison and delay adjustment logic in a single dedicated circuit rather than requiring complex distributed control.
Data Source
AI summary
A delay circuit includes a first delay line suitable for delaying a first clock by a delay value that is adjusted based on a delay control code; a delay control circuit suitable for comparing a phase of the first clock delayed through the first delay line with a phase of a second clock to generate the delay control code; and a second delay line having, based on a delay control code, a delay value corresponding to a half of the delay value of the first delay line.