Phase Interpolator Clock Recovery for Jitter-Stable Sampling
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Solution Overview
Problem
Conventional clock and data recovery circuits suffer from poor dynamic performance due to sudden phase jumps caused by phase drift, temperature changes, or power supply variations, leading to deteriorated jitter performance.
Innovation Solution
A phase interpolator for clock and data recovery circuits is designed, comprising an encoding circuit, multiplexers, a clock mixer, and differential to single-ended amplifiers, which samples data control and phase control signals to generate codes for selecting and weighting phase clocks, thereby adjusting the clock phase to maintain optimal sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock and data recovery circuits are used, then the basic clock recovery function is provided, but the dynamic performance deteriorates due to sudden phase jumps
Solution Approach 1:
The patent implements a dynamic phase adjustment mechanism where the phase interpolator continuously adapts the clock phase based on feedback from the data sampling process. The control unit dynamically selects and weights multiple phase clocks according to the detected sampling quality, enabling the system to track and compensate for phase drift in real-time, thereby resolving the contradiction between reliability and phase stability.
Solution Approach 2:
The patent employs a feedback mechanism where the control unit monitors the quality of data sampling and adjusts the phase interpolator's output accordingly. Based on the detected sampling results, the control unit generates control signals that modify the weighting coefficients of the phase clocks, creating a closed-loop system that continuously optimizes clock phase stability and prevents sudden phase jumps, thus improving dynamic performance while maintaining phase stability.
2Reliability
If phase drift compensation is implemented, then jitter performance improves, but the system complexity increases
Solution Approach 1:
The patent divides the phase compensation function into modular components: a phase interpolator with multiple independent phase clock inputs, a control unit with separate sampling and weighting functions, and individual weighting coefficients for each phase clock. This segmentation allows the complex phase drift compensation task to be distributed across multiple simple, manageable modules, reducing overall system complexity while maintaining effective jitter performance.
Solution Approach 2:
The control unit in the patent serves multiple functions: it samples the data signal, determines optimal sampling points, calculates weighting coefficients, and generates control signals for the phase interpolator. By consolidating these functions into a single multi-functional unit, the patent reduces the number of separate components needed, thereby managing system complexity while achieving effective phase drift compensation and jitter reduction.
Data Source
AI summary
A clock and data recovery circuit and a phase interpolator therefor are provided. The clock and data recovery circuit includes a phase-locked loop, a control unit and the phase interpolator, a receiving circuit, a serial-to-parallel conversion circuit. The phase interpolator is connected with the control unit of the clock and data recovery circuit, and the phase interpolator includes: an encoding circuit, two multiplexers, a clock mixer, and two differential to single-ended amplifiers. The control unit is configured to further control the encoding circuit to change a delay position for a clock outputted by the phase interpolator in a case that the data sampled in the current clock position is not the optimal sampled data, to lead or lag the clock, thereby forming a stable state in which the clock follows the data dynamically.