DAC-Weighted Phase Interpolator for Linear 360° Clock Sweeping
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Solution Overview
Problem
Phase interpolator circuits face errors such as phase shrinkage and integral nonlinearity error during clock phase sweeping operations, which affect the accuracy of timing measurements in high-speed circuit testing.
Innovation Solution
The implementation of a phase interpolator circuit that uses a digital-to-analog converter (DAC) to generate weighted clock signals from a set of reference phase clock signals, with a weighted averager circuit summing these signals to produce an output clock with interpolated phase, and a controller to adjust the weighting to sweep the phase through 360°, while minimizing errors through current mirror matching and calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a phase interpolator circuit is used to provide multiple phase-offset clock signals, then the ability to provide clock signals with desired phase relationships is improved, but phase shrinkage and integral nonlinearity errors occur during clock phase sweeping operations
Solution Approach 1:
The phase interpolator divides the phase range into multiple segments, each handled by a dedicated interpolator circuit. Each segment covers a specific phase range (e.g., 0-90 degrees, 90-180 degrees) with optimized weighting coefficients, reducing the cumulative phase error and nonlinearity across the full 360-degree range while maintaining adaptability for multiple phase-offset clock signals
Solution Approach 2:
The phase interpolator uses dynamically adjustable weighting coefficients that are updated based on the current phase segment. As the output phase changes, the controller switches between different sets of weighting coefficients to maintain linear phase progression and minimize integral nonlinearity error, enabling accurate timing measurements across the entire phase sweep range
2Measurement precision
If the clock phase is swept through 360 degrees using weighting adjustment, then the resolution of timing measurements is improved, but integral nonlinearity error increases
Solution Approach 1:
The system performs preliminary calibration to determine optimal weighting coefficients for each phase segment before actual operation. These pre-calculated coefficients are stored and applied during phase sweeping, ensuring that the phase progression remains linear and minimizing integral nonlinearity error while maintaining high measurement resolution
Solution Approach 2:
The phase interpolator changes the weighting coefficients as a function of the desired output phase. By dynamically adjusting these parameters based on the current phase segment and calibration data, the system maintains linear phase progression across the full 360-degree sweep, enabling both high resolution and accuracy in timing measurements
Data Source
AI summary
A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC output currents such that a sum of the first and second DAC output currents comprises a substantially constant current value, and a weighted averager circuit coupled to the MUX and the DAC. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal. The first clock signal may be weighted according to the first DAC output current and the second clock signal may be weighted according to the second DAC output current. Other apparatus, systems, and methods are disclosed.