Phase Interpolator Current Correction for Stable Clock Phase Spacing
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Solution Overview
Problem
Conventional phase interpolator circuits experience phase difference shifts between output clock signals, leading to reduced timing margins and hindered high-speed operations due to skew mismatch and non-linear phase variations.
Innovation Solution
A phase interpolator circuit with a first and second generation circuit generating intermediate currents based on input clock signals, a synthesis circuit for combining these currents, and a correction circuit to adjust current amounts using correction codes to maintain a constant phase difference, thereby correcting phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase interpolator circuits are used to generate output clock signals, then phase adjustment is achieved, but phase difference shifts occur between output clock signals leading to reduced timing margins
Solution Approach 1:
A correction circuit is introduced that receives feedback about the actual phase difference between output clock signals and generates correction currents to compensate for deviations from the target phase difference, thereby maintaining accurate timing margins
Solution Approach 2:
The invention dynamically adjusts the current amounts in the phase interpolator circuits by applying correction currents that modify the effective phase shift parameters, ensuring that phase differences remain constant despite process variations or temperature changes
2Productivity
If conventional phase interpolator circuits operate at high speeds, then productivity is improved, but phase errors increase due to skew mismatch and non-linear phase variations
Solution Approach 1:
The correction circuit pre-compensates for known phase errors by applying correction currents before the main phase interpolation operation, ensuring that even at high speeds the phase accuracy is maintained by anticipating and correcting for skew mismatch and non-linear variations
Solution Approach 2:
The system continuously monitors phase differences and applies real-time correction currents that counteract speed-related phase errors, allowing high-speed operation without sacrificing phase accuracy
Data Source
AI summary
A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.