Phase Interpolator Delay Circuit Without CML Summer Stages
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Solution Overview
Problem
Existing phase interpolators face issues with high power consumption, area inefficiency, and destructive interference due to current mode logic (CML) summers, which require additional converters for level shifting, increasing power, cost, and area requirements.
Innovation Solution
A phase interpolator with a variable delay circuit and a delay locked loop, utilizing multiplexers and delay cells with configurable PMOS and NMOS transistors, to generate phase-shifted outputs efficiently, reducing the need for separate timing signal lines and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If CML summer is used to generate phase shifted outputs, then phase shifting function is achieved, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates the CML summer component from the phase interpolator circuit. Instead of using CML summers to perform weighted summation of clock phases, the invention uses a delay-locked loop with multiplexers and delay cells to generate phase-shifted outputs directly, removing the source of high power consumption associated with CML logic.
Solution Approach 2:
The patent replaces the electronic CML summer mechanism with a timing-based delay-locked loop mechanism. Instead of using current-mode logic arithmetic operations, the invention uses controlled signal delay and multiplication (via DLL) to achieve phase interpolation, substituting one electronic mechanism with another that consumes less power.
2Measurement precision
If CML summer stages are increased to generate more phase shifted outputs, then phase resolution improves, but area increases
Solution Approach 1:
The delay-locked loop circuit serves multiple functions simultaneously: it generates multiple phase-shifted outputs, provides programmable phase resolution through the number of delay cells, and enables variable phase shifting ranges. A single DLL structure can generate N phase outputs by configuring N delay cells, eliminating the need for separate CML summer stages for each phase.
Solution Approach 2:
The patent introduces dynamic programmability to the phase interpolator through the delay-locked loop. The phase resolution and shifting range can be dynamically adjusted by reconfiguring the number of delay cells and their individual delay amounts, allowing the same hardware structure to adapt to different phase resolution requirements without increasing area.
3Power
If CML summer is used for phase interpolation, then phase shifting is achieved, but parasitic capacitance leads to high power consumption
Solution Approach 1:
The patent removes the CML summer component that introduces parasitic capacitance at its output nodes. By eliminating this component, the source of parasitic capacitance is removed, thereby reducing the harmful charging and discharging currents that lead to high power consumption in the phase interpolation process.
4Strength
If CML summer stages are used, then phase shifting function is achieved, but destructive interference reduces output swing
Solution Approach 1:
The patent avoids the destructive interference problem inherent in CML summers by using a different mechanism. Instead of summing currents that can interfere destructively, the delay-locked loop generates phase-shifted outputs through controlled delay elements that preserve signal integrity and full swing, converting the potential harm of signal degradation into a benefit of maintained output strength.
Data Source
AI summary
Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.